add div FSM as default for test_issuer in verilog and ilang gen

[soc.git] / src / soc / fu / compunits / compunits.py

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 455359f5d5aea651bd908bd59531463d4bc01e18..9cf44a9924faafd76eb5649b3978e7f656a9785a 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -72,7 +72,7 @@ from soc.fu.trap.pipeline import TrapBasePipe
 from soc.fu.trap.pipe_data import TrapPipeSpec
 
 from soc.fu.div.pipeline import DivBasePipe
-from soc.fu.div.pipe_data import DivPipeSpecDivPipeCore
+from soc.fu.div.pipe_data import DivPipeSpecFSMDivCore
 
 from soc.fu.mul.pipeline import MulBasePipe
 from soc.fu.mul.pipe_data import MulPipeSpec
@@ -162,7 +162,7 @@ class DivFunctionUnit(FunctionUnitBaseSingle):
     fnunit = Function.DIV
 
     def __init__(self, idx):
-        super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx)
+        super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx)
 
 
 class MulFunctionUnit(FunctionUnitBaseSingle):
@@ -185,17 +185,18 @@ class SPRFunctionUnit(FunctionUnitBaseSingle):
     def __init__(self, idx):
         super().__init__(SPRPipeSpec, SPRBasePipe, idx)
 
-# special-case
 
+# special-case: LD/ST conforms to the CompUnit API but is not a pipeline
 
 class LDSTFunctionUnit(LDSTCompUnit):
     fnunit = Function.LDST
 
     def __init__(self, pi, awid, idx):
+        alu_name = "ldst_%s%d" % (self.fnunit.name.lower(), idx)
         pspec = LDSTPipeSpec(id_wid=2)           # spec (NNNPipeSpec instance)
         opsubset = pspec.opsubsetkls             # get the operand subset class
         regspec = pspec.regspec                  # get the regspec
-        super().__init__(pi, regspec, awid, opsubset)
+        super().__init__(pi, regspec, awid, opsubset, name=alu_name)
 
 
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