msr and pc moved to "state" in PowerDecode2

[soc.git] / src / soc / fu / compunits / test / test_shiftrot_compunit.py

diff --git a/src/soc/fu/compunits/test/test_shiftrot_compunit.py b/src/soc/fu/compunits/test/test_shiftrot_compunit.py
index 1b8bf770f99bfcdc96eb52d6f1cebb57fc328755..d839e5ba7572d92ad45229c9ec3bb50f27010c76 100644 (file)
--- a/src/soc/fu/compunits/test/test_shiftrot_compunit.py
+++ b/src/soc/fu/compunits/test/test_shiftrot_compunit.py
@@ -4,6 +4,7 @@ from soc.decoder.power_enums import (XER_bits, Function)
 # XXX bad practice: use of global variables
 from soc.fu.shift_rot.test.test_pipe_caller import get_cu_inputs
 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
+from soc.config.endian import bigendian
 
 from soc.fu.compunits.compunits import ShiftRotFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
@@ -12,7 +13,7 @@ from soc.fu.compunits.test.test_compunit import TestRunner
 class ShiftRotTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, ShiftRotFunctionUnit, self,
-                         Function.SHIFT_ROT)
+                         Function.SHIFT_ROT, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to ShiftRotFunctionUnit input regspec
@@ -24,7 +25,7 @@ class ShiftRotTestRunner(TestRunner):
         """naming (res) must conform to ShiftRotFunctionUnit output regspec
         """
 
-        print ("outputs", repr(code), res)
+        print("outputs", repr(code), res)
 
         # RT
         out_reg_valid = yield dec2.e.write_reg.ok
@@ -40,7 +41,7 @@ class ShiftRotTestRunner(TestRunner):
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
-        print ("check extra output", repr(code), cridx_ok, cridx)
+        print("check extra output", repr(code), cridx_ok, cridx)
 
         if rc:
             self.assertEqual(cridx_ok, 1, code)
@@ -50,7 +51,7 @@ class ShiftRotTestRunner(TestRunner):
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value
             cr_actual = res['cr_a']
-            print ("CR", cridx, cr_expected, cr_actual)
+            print("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 
         # XER.ca
@@ -58,17 +59,17 @@ class ShiftRotTestRunner(TestRunner):
         if cry_out:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             xer_ca = res['xer_ca']
-            real_carry = xer_ca & 0b1 # XXX CO not CO32
+            real_carry = xer_ca & 0b1  # XXX CO not CO32
             self.assertEqual(expected_carry, real_carry, code)
             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-            real_carry32 = bool(xer_ca & 0b10) # XXX CO32
+            real_carry32 = bool(xer_ca & 0b10)  # XXX CO32
             self.assertEqual(expected_carry32, real_carry32, code)
 
 
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(ShiftRotTestRunner(ShiftRotTestCase.test_data))
+    suite.addTest(ShiftRotTestRunner(ShiftRotTestCase().test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)