from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
-from soc.config.endian import bigendian
-
-from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import Function
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
+
+from openpower.test.common import TestAccumulatorBase, ALUHelpers
+from openpower.util import mask_extend
from soc.fu.cr.pipeline import CRBasePipe
from soc.fu.cr.pipe_data import CRPipeSpec
import random
+from openpower.test.cr.cr_cases import CRTestCase
+
-# This test bench is a bit different than is usual. Initially when I
-# was writing it, I had all of the tests call a function to create a
-# device under test and simulator, initialize the dut, run the
-# simulation for ~2 cycles, and assert that the dut output what it
-# should have. However, this was really slow, since it needed to
-# create and tear down the dut and simulator for every test case.
-
-# Now, instead of doing that, every test case in ALUTestCase puts some
-# data into the test_data list below, describing the instructions to
-# be tested and the initial state. Once all the tests have been run,
-# test_data gets passed to TestRunner which then sets up the DUT and
-# simulator once, runs all the data through it, and asserts that the
-# results match the pseudocode sim at every cycle.
-
-# By doing this, I've reduced the time it takes to run the test suite
-# massively. Before, it took around 1 minute on my computer, now it
-# takes around 3 seconds
-
-
-class CRTestCase(TestAccumulatorBase):
-
- def case_crop(self):
- insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
- "crandc", "crorc"]
- for i in range(40):
- choice = random.choice(insns)
- ba = random.randint(0, 31)
- bb = random.randint(0, 31)
- bt = random.randint(0, 31)
- lst = [f"{choice} {ba}, {bb}, {bt}"]
- cr = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_crand(self):
- for i in range(20):
- lst = ["crand 0, 11, 13"]
- cr = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_1_mcrf(self):
- for i in range(20):
- src = random.randint(0, 7)
- dst = random.randint(0, 7)
- lst = [f"mcrf {src}, {dst}"]
- cr = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_0_mcrf(self):
- for i in range(8):
- lst = [f"mcrf 5, {i}"]
- cr = 0xfeff0001
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_mtcrf(self):
- for i in range(20):
- mask = random.randint(0, 255)
- lst = [f"mtcrf {mask}, 2"]
- cr = random.randint(0, (1 << 32)-1)
- initial_regs = [0] * 32
- initial_regs[2] = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_regs=initial_regs,
- initial_cr=cr)
-
- def case_mtocrf(self):
- for i in range(20):
- mask = 1 << random.randint(0, 7)
- lst = [f"mtocrf {mask}, 2"]
- cr = random.randint(0, (1 << 32)-1)
- initial_regs = [0] * 32
- initial_regs[2] = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_regs=initial_regs,
- initial_cr=cr)
-
- def case_mfcr(self):
- for i in range(5):
- lst = ["mfcr 2"]
- cr = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_mfocrf(self):
- for i in range(20):
- mask = 1 << random.randint(0, 7)
- lst = [f"mfocrf 2, {mask}"]
- cr = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_isel(self):
- for i in range(20):
- bc = random.randint(0, 31)
- lst = [f"isel 1, 2, 3, {bc}"]
- cr = random.randint(0, (1 << 32)-1)
- initial_regs = [0] * 32
- initial_regs[2] = random.randint(0, (1 << 64)-1)
- initial_regs[3] = random.randint(0, (1 << 64)-1)
- #initial_regs[2] = i*2
- #initial_regs[3] = i*2+1
- self.add_case(Program(lst, bigendian),
- initial_regs=initial_regs, initial_cr=cr)
-
- def case_setb(self):
- for i in range(20):
- bfa = random.randint(0, 7)
- lst = [f"setb 1, {bfa}"]
- cr = random.randint(0, (1 << 32)-1)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
-
- def case_regression_setb(self):
- lst = [f"setb 1, 6"]
- cr = random.randint(0, 0x66f6b106)
- self.add_case(Program(lst, bigendian), initial_cr=cr)
+class CRIlangCase(TestAccumulatorBase):
def case_ilang(self):
- pspec = CRPipeSpec(id_wid=2)
+ pspec = CRPipeSpec(id_wid=2, parent_pspec=None)
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
"""naming (res) must conform to CRFunctionUnit input regspec
"""
res = {}
- full_reg = yield dec2.e.do.read_cr_whole
+ full_reg = yield dec2.dec_cr_in.whole_reg.data
+ full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
+ full_cr_mask = mask_extend(full_reg, 8, 4)
# full CR
- print(sim.cr.get_range().value)
- if full_reg:
- res['full_cr'] = sim.cr.get_range().value
+ print(sim.cr.value)
+ if full_reg_ok:
+ res['full_cr'] = sim.cr.value & full_cr_mask
else:
- # CR A
- cr1_en = yield dec2.e.read_cr1.ok
- if cr1_en:
- cr1_sel = yield dec2.e.read_cr1.data
- res['cr_a'] = sim.crl[cr1_sel].get_range().value
- cr2_en = yield dec2.e.read_cr2.ok
- # CR B
- if cr2_en:
- cr2_sel = yield dec2.e.read_cr2.data
- res['cr_b'] = sim.crl[cr2_sel].get_range().value
- cr3_en = yield dec2.e.read_cr3.ok
- # CR C
- if cr3_en:
- cr3_sel = yield dec2.e.read_cr3.data
- res['cr_c'] = sim.crl[cr3_sel].get_range().value
-
- # RA/RC
- reg1_ok = yield dec2.e.read_reg1.ok
- if reg1_ok:
- data1 = yield dec2.e.read_reg1.data
- res['ra'] = sim.gpr(data1).value
-
- # RB (or immediate)
- reg2_ok = yield dec2.e.read_reg2.ok
- if reg2_ok:
- data2 = yield dec2.e.read_reg2.data
- res['rb'] = sim.gpr(data2).value
+ yield from ALUHelpers.get_sim_cr_a(res, sim, dec2) # CR A
+ yield from ALUHelpers.get_sim_cr_b(res, sim, dec2) # CR B
+ yield from ALUHelpers.get_sim_cr_c(res, sim, dec2) # CR C
+
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
print("get inputs", res)
return res
yield from ALUHelpers.set_int_rb(alu, dec2, inp)
def assert_outputs(self, alu, dec2, simulator, code):
- whole_reg = yield dec2.e.do.write_cr_whole
+ whole_reg_ok = yield dec2.dec_cr_out.whole_reg.ok
+ whole_reg_data = yield dec2.dec_cr_out.whole_reg.data
+ full_cr_mask = mask_extend(whole_reg_data, 8, 4)
+
cr_en = yield dec2.e.write_cr.ok
- if whole_reg:
- full_cr = yield alu.n.data_o.full_cr.data
- expected_cr = simulator.cr.get_range().value
- print(f"CR whole: expected {expected_cr:x}, actual: {full_cr:x}")
- self.assertEqual(expected_cr, full_cr, code)
+ if whole_reg_ok:
+ full_cr = yield alu.n.o_data.full_cr.data & full_cr_mask
+ expected_cr = simulator.cr.value
+ print("CR whole: expected %x, actual: %x mask: %x" %
+ (expected_cr, full_cr, full_cr_mask))
+ # HACK: only look at the bits that we expected to change
+ self.assertEqual(expected_cr & full_cr_mask, full_cr, code)
elif cr_en:
cr_sel = yield dec2.e.write_cr.data
- expected_cr = simulator.cr.get_range().value
+ expected_cr = simulator.cr.value
print(f"CR whole: {expected_cr:x}, sel {cr_sel}")
expected_cr = simulator.crl[cr_sel].get_range().value
- real_cr = yield alu.n.data_o.cr.data
+ real_cr = yield alu.n.o_data.cr.data
print(f"CR part: expected {expected_cr:x}, actual: {real_cr:x}")
self.assertEqual(expected_cr, real_cr, code)
- alu_out = yield alu.n.data_o.o.data
+ alu_out = yield alu.n.o_data.o.data
out_reg_valid = yield dec2.e.write_reg.ok
if out_reg_valid:
write_reg_idx = yield dec2.e.write_reg.data
yield instruction.eq(ins) # raw binary instr.
yield Settle()
yield from self.set_inputs(alu, pdecode2, sim)
- yield alu.p.valid_i.eq(1)
+ yield alu.p.i_valid.eq(1)
fn_unit = yield pdecode2.e.do.fn_unit
self.assertEqual(fn_unit, Function.CR.value, code)
yield
yield from sim.call(opname)
index = sim.pc.CIA.value//4
- vld = yield alu.n.valid_o
+ vld = yield alu.n.o_valid
while not vld:
yield
- vld = yield alu.n.valid_o
+ vld = yield alu.n.o_valid
yield
yield from self.assert_outputs(alu, pdecode2, sim, code)
+
def run_all(self):
m = Module()
comb = m.d.comb
instruction = Signal(32)
- pdecode = create_pdecode()
+ fn_name = "CR"
+ opkls = CRPipeSpec.opsubsetkls
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+ pdecode = pdecode2.dec
- pspec = CRPipeSpec(id_wid=2)
+ pspec = CRPipeSpec(id_wid=2, parent_pspec=None)
m.submodules.alu = alu = CRBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
- comb += alu.n.ready_i.eq(1)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.n.i_ready.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
yield from self.execute(alu, instruction, pdecode2, test)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("cr_simulator.vcd"):
sim.run()
unittest.main(exit=False)
suite = unittest.TestSuite()
suite.addTest(TestRunner(CRTestCase().test_data))
+ suite.addTest(TestRunner(CRIlangCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff