from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
-from nmigen.cli import rtlil
-import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+from nmigen.cli import rtlil
+import unittest
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import Function
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
+
+from openpower.test.common import TestAccumulatorBase, ALUHelpers
+from openpower.util import mask_extend
from soc.fu.cr.pipeline import CRBasePipe
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.cr.pipe_data import CRPipeSpec
import random
+from openpower.test.cr.cr_cases import CRTestCase
-class TestCase:
- def __init__(self, program, regs, sprs, cr, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
- self.cr = cr
-
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
-
-
-# This test bench is a bit different than is usual. Initially when I
-# was writing it, I had all of the tests call a function to create a
-# device under test and simulator, initialize the dut, run the
-# simulation for ~2 cycles, and assert that the dut output what it
-# should have. However, this was really slow, since it needed to
-# create and tear down the dut and simulator for every test case.
-
-# Now, instead of doing that, every test case in ALUTestCase puts some
-# data into the test_data list below, describing the instructions to
-# be tested and the initial state. Once all the tests have been run,
-# test_data gets passed to TestRunner which then sets up the DUT and
-# simulator once, runs all the data through it, and asserts that the
-# results match the pseudocode sim at every cycle.
-
-# By doing this, I've reduced the time it takes to run the test suite
-# massively. Before, it took around 1 minute on my computer, now it
-# takes around 3 seconds
-
-test_data = []
-
-
-class CRTestCase(FHDLTestCase):
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={},
- initial_cr=0):
- tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
- self.test_name)
- test_data.append(tc)
-
- def test_crop(self):
- insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
- "crandc", "crorc"]
- for i in range(40):
- choice = random.choice(insns)
- ba = random.randint(0, 31)
- bb = random.randint(0, 31)
- bt = random.randint(0, 31)
- lst = [f"{choice} {ba}, {bb}, {bt}"]
- cr = random.randint(0, 7)
- self.run_tst_program(Program(lst), initial_cr=cr)
-
- def test_mcrf(self):
- lst = ["mcrf 0, 5"]
- cr = 0xffff0000
- self.run_tst_program(Program(lst), initial_cr=cr)
-
- def test_mtcrf(self):
- for i in range(20):
- mask = random.randint(0, 255)
- lst = [f"mtcrf {mask}, 2"]
- cr = random.randint(0, (1<<32)-1)
- initial_regs = [0] * 32
- initial_regs[2] = random.randint(0, (1<<32)-1)
- self.run_tst_program(Program(lst), initial_regs=initial_regs,
- initial_cr=cr)
- def test_mtocrf(self):
- for i in range(20):
- mask = 1<<random.randint(0, 7)
- lst = [f"mtocrf {mask}, 2"]
- cr = random.randint(0, (1<<32)-1)
- initial_regs = [0] * 32
- initial_regs[2] = random.randint(0, (1<<32)-1)
- self.run_tst_program(Program(lst), initial_regs=initial_regs,
- initial_cr=cr)
-
- def test_mfcr(self):
- for i in range(5):
- lst = ["mfcr 2"]
- cr = random.randint(0, (1<<32)-1)
- self.run_tst_program(Program(lst), initial_cr=cr)
-
- def test_mfocrf(self):
- for i in range(20):
- mask = 1<<random.randint(0, 7)
- lst = [f"mfocrf 2, {mask}"]
- cr = random.randint(0, (1<<32)-1)
- self.run_tst_program(Program(lst), initial_cr=cr)
-
-
- def test_ilang(self):
- rec = CompALUOpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+
+class CRIlangCase(TestAccumulatorBase):
+
+ def case_ilang(self):
+ pspec = CRPipeSpec(id_wid=2, parent_pspec=None)
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
f.write(vl)
-class TestRunner(FHDLTestCase):
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to CRFunctionUnit input regspec
+ """
+ res = {}
+ full_reg = yield dec2.dec_cr_in.whole_reg.data
+ full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
+ full_cr_mask = mask_extend(full_reg, 8, 4)
+
+ # full CR
+ print(sim.cr.value)
+ if full_reg_ok:
+ res['full_cr'] = sim.cr.value & full_cr_mask
+ else:
+ yield from ALUHelpers.get_sim_cr_a(res, sim, dec2) # CR A
+ yield from ALUHelpers.get_sim_cr_b(res, sim, dec2) # CR B
+ yield from ALUHelpers.get_sim_cr_c(res, sim, dec2) # CR C
+
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
+
+ print("get inputs", res)
+ return res
+
+
+class TestRunner(unittest.TestCase):
def __init__(self, test_data):
super().__init__("run_all")
self.test_data = test_data
def set_inputs(self, alu, dec2, simulator):
- yield alu.p.data_i.cr.eq(simulator.cr.get_range().value)
-
- reg3_ok = yield dec2.e.read_reg3.ok
- if reg3_ok:
- reg3_sel = yield dec2.e.read_reg3.data
- reg3 = simulator.gpr(reg3_sel).value
- yield alu.p.data_i.a.eq(reg3)
+ inp = yield from get_cu_inputs(dec2, simulator)
+ yield from ALUHelpers.set_full_cr(alu, dec2, inp)
+ yield from ALUHelpers.set_cr_a(alu, dec2, inp)
+ yield from ALUHelpers.set_cr_b(alu, dec2, inp)
+ yield from ALUHelpers.set_cr_c(alu, dec2, inp)
+ yield from ALUHelpers.set_int_ra(alu, dec2, inp)
+ yield from ALUHelpers.set_int_rb(alu, dec2, inp)
+
+ def assert_outputs(self, alu, dec2, simulator, code):
+ whole_reg_ok = yield dec2.dec_cr_out.whole_reg.ok
+ whole_reg_data = yield dec2.dec_cr_out.whole_reg.data
+ full_cr_mask = mask_extend(whole_reg_data, 8, 4)
+
+ cr_en = yield dec2.e.write_cr.ok
+ if whole_reg_ok:
+ full_cr = yield alu.n.o_data.full_cr.data & full_cr_mask
+ expected_cr = simulator.cr.value
+ print("CR whole: expected %x, actual: %x mask: %x" %
+ (expected_cr, full_cr, full_cr_mask))
+ # HACK: only look at the bits that we expected to change
+ self.assertEqual(expected_cr & full_cr_mask, full_cr, code)
+ elif cr_en:
+ cr_sel = yield dec2.e.write_cr.data
+ expected_cr = simulator.cr.value
+ print(f"CR whole: {expected_cr:x}, sel {cr_sel}")
+ expected_cr = simulator.crl[cr_sel].get_range().value
+ real_cr = yield alu.n.o_data.cr.data
+ print(f"CR part: expected {expected_cr:x}, actual: {real_cr:x}")
+ self.assertEqual(expected_cr, real_cr, code)
+ alu_out = yield alu.n.o_data.o.data
+ out_reg_valid = yield dec2.e.write_reg.ok
+ if out_reg_valid:
+ write_reg_idx = yield dec2.e.write_reg.data
+ expected = simulator.gpr(write_reg_idx).value
+ print(f"expected {expected:x}, actual: {alu_out:x}")
+ self.assertEqual(expected, alu_out, code)
+
+ def execute(self, alu, instruction, pdecode2, test):
+ program = test.program
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+ test.msr,
+ bigendian=bigendian)
+ gen = program.generate_instructions()
+ instructions = list(zip(gen, program.assembly.splitlines()))
+
+ index = sim.pc.CIA.value//4
+ while index < len(instructions):
+ ins, code = instructions[index]
+
+ print("0x{:X}".format(ins & 0xffffffff))
+ print(code)
+
+ # ask the decoder to decode this binary data (endian'd)
+ yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
+ yield instruction.eq(ins) # raw binary instr.
+ yield Settle()
+ yield from self.set_inputs(alu, pdecode2, sim)
+ yield alu.p.i_valid.eq(1)
+ fn_unit = yield pdecode2.e.do.fn_unit
+ self.assertEqual(fn_unit, Function.CR.value, code)
+ yield
+ opname = code.split(' ')[0]
+ yield from sim.call(opname)
+ index = sim.pc.CIA.value//4
+
+ vld = yield alu.n.o_valid
+ while not vld:
+ yield
+ vld = yield alu.n.o_valid
+ yield
+ yield from self.assert_outputs(alu, pdecode2, sim, code)
def run_all(self):
m = Module()
comb = m.d.comb
instruction = Signal(32)
- pdecode = create_pdecode()
-
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ fn_name = "CR"
+ opkls = CRPipeSpec.opsubsetkls
- rec = CompALUOpSubset()
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+ pdecode = pdecode2.dec
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = CRPipeSpec(id_wid=2, parent_pspec=None)
m.submodules.alu = alu = CRBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
- comb += alu.p.valid_i.eq(1)
- comb += alu.n.ready_i.eq(1)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.n.i_ready.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
sim.add_clock(1e-6)
+
def process():
for test in self.test_data:
print(test.name)
- program = test.program
- self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
-
- index = simulator.pc.CIA.value//4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield Settle()
- yield from self.set_inputs(alu, pdecode2, simulator)
- fn_unit = yield pdecode2.e.fn_unit
- self.assertEqual(fn_unit, Function.CR.value, code)
- yield
- opname = code.split(' ')[0]
- yield from simulator.call(opname)
- index = simulator.pc.CIA.value//4
-
- vld = yield alu.n.valid_o
- while not vld:
- yield
- vld = yield alu.n.valid_o
- yield
- cr_out = yield pdecode2.e.output_cr
- if cr_out:
- cr_expected = simulator.cr.get_range().value
- cr_real = yield alu.n.data_o.cr
- msg = f"real: {cr_expected:x}, actual: {cr_real:x}"
- msg += " code: %s" % code
- self.assertEqual(cr_expected, cr_real, msg)
-
- reg_out = yield pdecode2.e.write_reg.ok
- if reg_out:
- reg_sel = yield pdecode2.e.write_reg.data
- reg_data = simulator.gpr(reg_sel).value
- output = yield alu.n.data_o.o
- msg = f"real: {reg_data:x}, actual: {output:x}"
- self.assertEqual(reg_data, output)
+ with self.subTest(test.name):
+ yield from self.execute(alu, instruction, pdecode2, test)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("cr_simulator.vcd"):
sim.run()
- def check_extra_alu_outputs(self, alu, dec2, sim):
- rc = yield dec2.e.rc.data
- if rc:
- cr_expected = sim.crl[0].get_range().value
- cr_actual = yield alu.n.data_o.cr0
- self.assertEqual(cr_expected, cr_actual)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(CRTestCase().test_data))
+ suite.addTest(TestRunner(CRIlangCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff