from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.isa.all import ISA
+from soc.fu.test.common import TestCase
from soc.fu.cr.pipeline import CRBasePipe
-from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.cr.pipe_data import CRPipeSpec
import random
-class TestCase:
- def __init__(self, program, regs, sprs, cr, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
- self.cr = cr
-
# This test bench is a bit different than is usual. Initially when I
# was writing it, I had all of the tests call a function to create a
def __init__(self, name):
super().__init__(name)
self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={},
+
+ def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
initial_cr=0):
- tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
- self.test_name)
+ tc = TestCase(prog, self.test_name,
+ regs=initial_regs, sprs=initial_sprs, cr=initial_cr)
test_data.append(tc)
def test_crop(self):
lst = [f"mfocrf 2, {mask}"]
cr = random.randint(0, (1<<32)-1)
self.run_tst_program(Program(lst), initial_cr=cr)
-
+
+ def test_isel(self):
+ for i in range(20):
+ bc = random.randint(0, 31)
+ lst = [f"isel 1, 2, 3, {bc}"]
+ cr = random.randint(0, (1<<32)-1)
+ initial_regs = [0] * 32
+ initial_regs[2] = random.randint(0, (1<<64)-1)
+ initial_regs[3] = random.randint(0, (1<<64)-1)
+ self.run_tst_program(Program(lst),
+ initial_regs=initial_regs, initial_cr=cr)
+
+ def test_setb(self):
+ for i in range(20):
+ bfa = random.randint(0, 7)
+ lst = [f"setb 1, {bfa}"]
+ cr = random.randint(0, (1<<32)-1)
+ self.run_tst_program(Program(lst), initial_cr=cr)
+
+
def test_ilang(self):
pspec = CRPipeSpec(id_wid=2)
f.write(vl)
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to CRFunctionUnit input regspec
+ """
+ res = {}
+ full_reg = yield dec2.e.read_cr_whole
+
+ # full CR
+ print(sim.cr.get_range().value)
+ if full_reg:
+ res['full_cr'] = sim.cr.get_range().value
+ else:
+ # CR A
+ cr1_en = yield dec2.e.read_cr1.ok
+ if cr1_en:
+ cr1_sel = yield dec2.e.read_cr1.data
+ res['cr_a'] = sim.crl[cr1_sel].get_range().value
+ cr2_en = yield dec2.e.read_cr2.ok
+ # CR B
+ if cr2_en:
+ cr2_sel = yield dec2.e.read_cr2.data
+ res['cr_b'] = sim.crl[cr2_sel].get_range().value
+ cr3_en = yield dec2.e.read_cr3.ok
+ # CR C
+ if cr3_en:
+ cr3_sel = yield dec2.e.read_cr3.data
+ res['cr_c'] = sim.crl[cr3_sel].get_range().value
+
+ # RA/RC
+ reg1_ok = yield dec2.e.read_reg1.ok
+ if reg1_ok:
+ data1 = yield dec2.e.read_reg1.data
+ res['ra'] = sim.gpr(data1).value
+
+ # RB (or immediate)
+ reg2_ok = yield dec2.e.read_reg2.ok
+ if reg2_ok:
+ data2 = yield dec2.e.read_reg2.data
+ res['rb'] = sim.gpr(data2).value
+
+ print ("get inputs", res)
+ return res
+
+
class TestRunner(FHDLTestCase):
def __init__(self, test_data):
super().__init__("run_all")
self.test_data = test_data
def set_inputs(self, alu, dec2, simulator):
- full_reg = yield dec2.e.read_cr_whole
-
- print(simulator.cr.get_range().value)
- if full_reg:
- yield alu.p.data_i.full_cr.eq(simulator.cr.get_range().value)
+ inp = yield from get_cu_inputs(dec2, simulator)
+ if 'full_cr' in inp:
+ yield alu.p.data_i.full_cr.eq(inp['full_cr'])
else:
- cr1_en = yield dec2.e.read_cr1.ok
- if cr1_en:
- cr1_sel = yield dec2.e.read_cr1.data
- cr1 = simulator.crl[cr1_sel].get_range().value
- yield alu.p.data_i.cr_a.eq(cr1)
- cr2_en = yield dec2.e.read_cr2.ok
- if cr2_en:
- cr2_sel = yield dec2.e.read_cr2.data
- cr2 = simulator.crl[cr2_sel].get_range().value
- yield alu.p.data_i.cr_b.eq(cr2)
- cr3_en = yield dec2.e.read_cr3.ok
- if cr3_en:
- cr3_sel = yield dec2.e.read_cr3.data
- cr3 = simulator.crl[cr3_sel].get_range().value
- yield alu.p.data_i.cr_c.eq(cr3)
-
- reg3_ok = yield dec2.e.read_reg3.ok
- if reg3_ok:
- reg3_sel = yield dec2.e.read_reg3.data
- reg3 = simulator.gpr(reg3_sel).value
- yield alu.p.data_i.a.eq(reg3)
-
- def assert_outputs(self, alu, dec2, simulator):
+ yield alu.p.data_i.full_cr.eq(0)
+ if 'cr_a' in inp:
+ yield alu.p.data_i.cr_a.eq(inp['cr_a'])
+ if 'cr_b' in inp:
+ yield alu.p.data_i.cr_b.eq(inp['cr_b'])
+ if 'cr_c' in inp:
+ yield alu.p.data_i.cr_c.eq(inp['cr_c'])
+ if 'ra' in inp:
+ yield alu.p.data_i.ra.eq(inp['ra'])
+ else:
+ yield alu.p.data_i.ra.eq(0)
+ if 'rb' in inp:
+ yield alu.p.data_i.rb.eq(inp['rb'])
+ else:
+ yield alu.p.data_i.rb.eq(0)
+
+ def assert_outputs(self, alu, dec2, simulator, code):
whole_reg = yield dec2.e.write_cr_whole
cr_en = yield dec2.e.write_cr.ok
if whole_reg:
- full_cr = yield alu.n.data_o.full_cr
+ full_cr = yield alu.n.data_o.full_cr.data
expected_cr = simulator.cr.get_range().value
- self.assertEqual(expected_cr, full_cr)
+ self.assertEqual(expected_cr, full_cr, code)
elif cr_en:
cr_sel = yield dec2.e.write_cr.data
expected_cr = simulator.crl[cr_sel].get_range().value
- real_cr = yield alu.n.data_o.cr_o
- self.assertEqual(expected_cr, real_cr)
-
+ real_cr = yield alu.n.data_o.cr.data
+ self.assertEqual(expected_cr, real_cr, code)
+ alu_out = yield alu.n.data_o.o.data
+ out_reg_valid = yield dec2.e.write_reg.ok
+ if out_reg_valid:
+ write_reg_idx = yield dec2.e.write_reg.data
+ expected = simulator.gpr(write_reg_idx).value
+ print(f"expected {expected:x}, actual: {alu_out:x}")
+ self.assertEqual(expected, alu_out, code)
def run_all(self):
m = Module()
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
- index = simulator.pc.CIA.value//4
+ index = sim.pc.CIA.value//4
while index < len(instructions):
ins, code = instructions[index]
yield pdecode2.dec.bigendian.eq(0) # little / big?
yield instruction.eq(ins) # raw binary instr.
yield Settle()
- yield from self.set_inputs(alu, pdecode2, simulator)
+ yield from self.set_inputs(alu, pdecode2, sim)
yield alu.p.valid_i.eq(1)
fn_unit = yield pdecode2.e.fn_unit
self.assertEqual(fn_unit, Function.CR.value, code)
- yield
+ yield
opname = code.split(' ')[0]
- yield from simulator.call(opname)
- index = simulator.pc.CIA.value//4
+ yield from sim.call(opname)
+ index = sim.pc.CIA.value//4
vld = yield alu.n.valid_o
while not vld:
yield
vld = yield alu.n.valid_o
yield
- yield from self.assert_outputs(alu, pdecode2, simulator)
+ yield from self.assert_outputs(alu, pdecode2, sim, code)
sim.add_sync_process(process)
with sim.write_vcd("simulator.vcd", "simulator.gtkw",
traces=[]):
sim.run()
- def check_extra_alu_outputs(self, alu, dec2, sim):
- rc = yield dec2.e.rc.data
- if rc:
- cr_expected = sim.crl[0].get_range().value
- cr_actual = yield alu.n.data_o.cr0
- self.assertEqual(cr_expected, cr_actual)
if __name__ == "__main__":
projects / soc.git / blobdiff