Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / div / setup_stage.py

diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py
index 25daa201b8dc1e0b1dd80413b87d77683a47e3f8..5fe049786ae9074e30e39a48fe4939b0e7382ba3 100644 (file)
--- a/src/soc/fu/div/setup_stage.py
+++ b/src/soc/fu/div/setup_stage.py
@@ -3,12 +3,12 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.div.pipe_data import DIVInputData
-from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.fu.div.pipe_data import DivInputData
+from ieee754.part.partsig import SimdSignal
+from openpower.decoder.power_enums import MicrOp
 
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
 from soc.fu.div.pipe_data import CoreInputData
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation
 from nmutil.util import eq32
@@ -21,12 +21,13 @@ class DivSetupStage(PipeModBase):
         self.fields.create_specs()
 
     def ispec(self):
-        return DIVInputData(self.pspec)
+        return DivInputData(self.pspec)
 
     def ospec(self):
         return CoreInputData(self.pspec)
 
     def elaborate(self, platform):
+        XLEN = self.pspec.XLEN
         m = Module()
         comb = m.d.comb
         # convenience variables
@@ -41,23 +42,25 @@ class DivSetupStage(PipeModBase):
         comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem))
 
         # work out if a/b are negative (check 32-bit / signed)
-        comb += dividend_neg_o.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
-        comb += divisor_neg_o.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
+        comb += dividend_neg_o.eq(Mux(op.is_32bit,
+                                      a[31], a[XLEN-1]) & op.is_signed)
+        comb += divisor_neg_o.eq(Mux(op.is_32bit,
+                                      b[31], b[XLEN-1]) & op.is_signed)
 
         # negation of a 64-bit value produces the same lower 32-bit
         # result as negation of just the lower 32-bits, so we don't
         # need to do anything special before negating
-        abs_dor = Signal(64, reset_less=True) # absolute of divisor
-        abs_dend = Signal(64, reset_less=True) # absolute of dividend
+        abs_dor = Signal(XLEN, reset_less=True)  # absolute of divisor
+        abs_dend = Signal(XLEN, reset_less=True)  # absolute of dividend
         comb += abs_dor.eq(Mux(divisor_neg_o, -b, b))
         comb += abs_dend.eq(Mux(dividend_neg_o, -a, a))
 
         # check for absolute overflow condition (32/64)
         comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor)
-                                        & (op.insn_type == InternalOp.OP_DIVE))
+                                        & (op.insn_type == MicrOp.OP_DIVE))
 
         comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32])
-                                        & (op.insn_type == InternalOp.OP_DIVE))
+                                        & (op.insn_type == MicrOp.OP_DIVE))
 
         # set divisor based on 32/64 bit mode (must be absolute)
         comb += eq32(op.is_32bit, divisor_o, abs_dor)
@@ -66,18 +69,18 @@ class DivSetupStage(PipeModBase):
         comb += self.o.div_by_zero.eq(divisor_o == 0)
 
         ##########################
-        # main switch for DIV
+        # main switch for Div
 
         with m.Switch(op.insn_type):
             # div/mod takes straight (absolute) dividend
-            with m.Case(InternalOp.OP_DIV, InternalOp.OP_MOD):
+            with m.Case(MicrOp.OP_DIV, MicrOp.OP_MOD):
                 comb += eq32(op.is_32bit, dividend_o, abs_dend)
             # extended div shifts dividend up
-            with m.Case(InternalOp.OP_DIVE):
+            with m.Case(MicrOp.OP_DIVE):
                 with m.If(op.is_32bit):
                     comb += dividend_o.eq(abs_dend[0:32] << 32)
                 with m.Else():
-                    comb += dividend_o.eq(abs_dend[0:64] << 64)
+                    comb += dividend_o.eq(abs_dend[0:XLEN] << XLEN)
 
         ###### sticky overflow and context, both pass-through #####