set initial_sprs, cleanup mfspr testprog

[soc.git] / src / soc / fu / mmu / pipe_data.py

diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py
index 5affde652cdb953e5c62ac5422556801b1c94654..1b7066d4dfabfff72640f1c31e23246db4efa28d 100644 (file)
--- a/src/soc/fu/mmu/pipe_data.py
+++ b/src/soc/fu/mmu/pipe_data.py
@@ -2,9 +2,8 @@
 
 Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.
 
-Note: RB is *redirected* (in the decoder CSV files) to the field that
-happens, here, to be named "ra"!  yes wonderfully confusing.  similar
-thing goes on with shift_rot.
+Interestingly none of the MMU instructions use RA, they all use RB.
+except dcbz which uses (RA|0)
 
 Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=491
@@ -18,19 +17,19 @@ from soc.fu.alu.pipe_data import CommonPipeSpec
 
 class MMUInputData(IntegerData):
     regspec = [('INT', 'ra', '0:63'),        # RA
+               ('INT', 'rb', '0:63'),        # RB
                ('SPR', 'spr1', '0:63'),      # MMU (slow)
-               ('FAST', 'fast1', '0:63'),    # MMU (fast: LR, CTR etc)
                ]   
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
         self.a = self.ra
+        self.b = self.rb
 
 
 class MMUOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('SPR', 'spr1', '0:63'),     # MMU (slow)
-               ('FAST', 'fast1', '0:63'),   # MMU (fast: LR, CTR etc)
                ]
     def __init__(self, pspec):
         super().__init__(pspec, True)