from soc.fu.test.common import (
TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
-from soc.fu.spr.pipeline import SPRBasePipe
-from soc.fu.spr.pipe_data import SPRPipeSpec
+#from soc.fu.spr.pipeline import SPRBasePipe
+#from soc.fu.spr.pipe_data import SPRPipeSpec
+from soc.fu.mmu.fsm import FSMMMUStage
+from soc.fu.mmu.pipe_data import MMUPipeSpec
import random
+from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
+ set_alu_inputs, DivTestHelper)
+
+import power_instruction_analyzer as pia
+
+debughang = 1
+
+def set_fsm_inputs(alu, dec2, sim):
+ # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
+ # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
+ # and place it into data_i.b
+
+ print("Error here")
+ inp = yield from get_cu_inputs(dec2, sim)
+ # set int registers a and b
+ yield from ALUHelpers.set_int_ra(alu, dec2, inp)
+ yield from ALUHelpers.set_int_rb(alu, dec2, inp)
+ # TODO set spr register
+ # yield from ALUHelpers.set_spr_spr1(alu, dec2, inp)
+
+ overflow = None
+ a=None
+ b=None
+ # TODO
+ if 'xer_so' in inp:
+ print("xer_so::::::::::::::::::::::::::::::::::::::::::::::::")
+ so = inp['xer_so']
+ print(so)
+ overflow = pia.OverflowFlags(so=bool(so),
+ ov=False,
+ ov32=False)
+ if 'ra' in inp:
+ a = inp['ra']
+ if 'rb' in inp:
+ b = inp['rb']
+ print(inp)
+ return pia.InstructionInput(ra=a, rb=b, overflow=overflow)
+
+
+def check_fsm_outputs(fsm, pdecode2, sim, code):
+ # check that MMUOutputData is correct
+ return None #TODO
+
+#incomplete test - connect fsm inputs first
+class MMUTestCase(TestAccumulatorBase):
+ # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
+ # other instructions here -> must be load/store
+
+ #before running the test case: set DISR and DAR
+
+ def case_mfspr_after_invalid_load(self):
+ lst = [ # TODO -- set SPR on both sinulator and port interface
+ "mfspr 1, 18", # DSISR to reg 1
+ "mfspr 2, 19", # DAR to reg 2
+ # TODO -- verify returned sprvals
+ ]
-#incomplete test - not working yet
-class MMUTestCase(TestAccumulatorBase):
-
- def case_1_mmu(self):
- # test case for MTSPR, MFSPR, DCBZ and TLBIE.
- lst = ["mfspr 1, 26", # SRR0
- "mfspr 2, 27", # SRR1
- "mfspr 3, 8", # LR
- "mfspr 4, 1", ] # XER
initial_regs = [0] * 32
- initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
- 'XER': 0xe00c0000}
+
+ initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs)
- def case_ilang(self):
- pspec = SPRPipeSpec(id_wid=2)
- alu = SPRBasePipe(pspec)
- vl = rtlil.convert(alu, ports=alu.ports())
- with open("trap_pipeline.il", "w") as f:
- f.write(vl)
+ #def case_ilang(self):
+ # pspec = SPRPipeSpec(id_wid=2)
+ # alu = SPRBasePipe(pspec)
+ # vl = rtlil.convert(alu, ports=alu.ports())
+ # with open("trap_pipeline.il", "w") as f:
+ # f.write(vl)
class TestRunner(unittest.TestCase):
super().__init__("run_all")
self.test_data = test_data
- def execute(self, alu, instruction, pdecode2, test):
+ def check_fsm_outputs(self, alu, dec2, sim, code, pia_res):
+
+ rc = yield dec2.e.do.rc.data
+ cridx_ok = yield dec2.e.write_cr.ok
+ cridx = yield dec2.e.write_cr.data
+
+ print("check extra output", repr(code), cridx_ok, cridx)
+ if rc:
+ self.assertEqual(cridx, 0, code)
+
+ sim_o = {}
+ res = {}
+
+ #MMUOutputData does not have xer
+
+ yield from ALUHelpers.get_cr_a(res, alu, dec2)
+ #yield from ALUHelpers.get_xer_ov(res, alu, dec2)
+ yield from ALUHelpers.get_int_o(res, alu, dec2)
+ #yield from ALUHelpers.get_xer_so(res, alu, dec2)
+
+
+ print("res output", res)
+
+ yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
+ #yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
+ #yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
+
+ print("sim output", sim_o)
+
+ print("power-instruction-analyzer result:")
+ print(pia_res)
+ #if pia_res is not None:
+ # with self.subTest(check="pia", sim_o=sim_o, pia_res=str(pia_res)):
+ # pia_o = pia_res_to_output(pia_res)
+ # ALUHelpers.check_int_o(self, res, pia_o, code)
+ # ALUHelpers.check_cr_a(self, res, pia_o, code)
+ # #ALUHelpers.check_xer_ov(self, res, pia_o, code)
+ # #ALUHelpers.check_xer_so(self, res, pia_o, code)
+
+ with self.subTest(check="sim", sim_o=sim_o, pia_res=str(pia_res)):
+ #ALUHelpers.check_int_o(self, res, sim_o, code) # mmu is not an alu
+ ALUHelpers.check_cr_a(self, res, sim_o, code)
+ #ALUHelpers.check_xer_ov(self, res, sim_o, code)
+ #ALUHelpers.check_xer_so(self, res, sim_o, code)
+
+ #oe = yield dec2.e.do.oe.oe
+ #oe_ok = yield dec2.e.do.oe.ok
+ #print("oe, oe_ok", oe, oe_ok)
+ #if not oe or not oe_ok:
+ # # if OE not enabled, XER SO and OV must not be activated
+ # so_ok = yield alu.n.data_o.xer_so.ok
+ # ov_ok = yield alu.n.data_o.xer_ov.ok
+ # print("so, ov", so_ok, ov_ok)
+ # self.assertEqual(ov_ok, False, code)
+ # self.assertEqual(so_ok, False, code)
+
+ def execute(self, fsm, instruction, pdecode2, test):
program = test.program
sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
test.mem, test.msr,
print("dec2 spr/fast in", fast_out, spr_out)
fn_unit = yield pdecode2.e.do.fn_unit
- self.assertEqual(fn_unit, Function.SPR.value)
- alu_o = yield from set_alu_inputs(alu, pdecode2, sim)
+ #FIXME this fails -- self.assertEqual(fn_unit, Function.SPR.value)
+ pia_res = yield from set_fsm_inputs(fsm, pdecode2, sim)
yield
opname = code.split(' ')[0]
yield from sim.call(opname)
index = pc//4
print("pc after %08x" % (pc))
- vld = yield alu.n.valid_o
+ vld = yield fsm.n.valid_o #fsm
while not vld:
yield
- vld = yield alu.n.valid_o
+ if debughang: print("not valid -- hang")
+ vld = yield fsm.n.valid_o
+ if debughang==2: vld=1
yield
- yield from self.check_alu_outputs(alu, pdecode2, sim, code)
+ yield from self.check_fsm_outputs(fsm, pdecode2, sim, code, pia_res)
def run_all(self):
m = Module()
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = SPRPipeSpec(id_wid=2)
- m.submodules.alu = alu = SPRBasePipe(pspec)
+ pspec = MMUPipeSpec(id_wid=2)
+ m.submodules.fsm = fsm = FSMMMUStage(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
- comb += alu.p.valid_i.eq(1)
- comb += alu.n.ready_i.eq(1)
+ #FIXME connect fsm inputs
+
+ comb += fsm.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += fsm.p.valid_i.eq(1)
+ comb += fsm.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
print("sprs", test.sprs)
program = test.program
with self.subTest(test.name):
- yield from self.execute(alu, instruction, pdecode2, test)
+ yield from self.execute(fsm, instruction, pdecode2, test)
sim.add_sync_process(process)
with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
traces=[]):
sim.run()
- def check_alu_outputs(self, alu, dec2, sim, code):
-
- rc = yield dec2.e.do.rc.data
- cridx_ok = yield dec2.e.write_cr.ok
- cridx = yield dec2.e.write_cr.data
-
- print("check extra output", repr(code), cridx_ok, cridx)
- if rc:
- self.assertEqual(cridx, 0, code)
-
- sim_o = {}
- res = {}
-
- yield from ALUHelpers.get_int_o(res, alu, dec2)
- yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
- yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
- yield from ALUHelpers.get_xer_ov(res, alu, dec2)
- yield from ALUHelpers.get_xer_ca(res, alu, dec2)
- yield from ALUHelpers.get_xer_so(res, alu, dec2)
-
- print("output", res)
-
- yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
- yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
- yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
- yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
- yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
-
- print("sim output", sim_o)
-
- ALUHelpers.check_xer_ov(self, res, sim_o, code)
- ALUHelpers.check_xer_ca(self, res, sim_o, code)
- ALUHelpers.check_xer_so(self, res, sim_o, code)
- ALUHelpers.check_int_o(self, res, sim_o, code)
- ALUHelpers.check_fast_spr1(self, res, sim_o, code)
- ALUHelpers.check_slow_spr1(self, res, sim_o, code)
-
-
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(SPRTestCase().test_data))
+ suite.addTest(TestRunner(MMUTestCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff