from nmutil.concurrentunit import PipeContext
from nmutil.dynamicpipe import SimpleHandshakeRedir
from nmigen import Signal
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
from soc.fu.regspec import get_regspec_bitwidth
-class IntegerData:
- """IntegerData: base class for all pipeline data structures
+class FUBaseData:
+ """FUBaseData: base class for all pipeline data structures
see README.md for explanation of parameters and purpose.
pipeline *to* output) must have it set to "True".
"""
- def __init__(self, pspec, output):
+ def __init__(self, pspec, output, exc_kls=None):
self.ctx = PipeContext(pspec) # context for ReservationStation usage
self.muxid = self.ctx.muxid
self.data = []
self.is_output = output
+ # take regspec and create data attributes (in or out)
+ # TODO: use widspec to create reduced bit mapping.
for i, (regfile, regname, widspec) in enumerate(self.regspec):
wid = get_regspec_bitwidth([self.regspec], 0, i)
if output:
sig = Signal(wid, name=regname, reset_less=True)
setattr(self, regname, sig)
self.data.append(sig)
+ # optional exception type
+ if exc_kls is not None:
+ name = "exc_o" if output else "exc_i"
+ self.exception = exc_kls(name=name)
def __iter__(self):
yield from self.ctx
yield from self.data
+ if hasattr(self, "exception"):
+ yield from self.exception.ports()
def eq(self, i):
eqs = [self.ctx.eq(i.ctx)]
(repr(self), repr(i), repr(self.data), repr(i.data))
for j in range(len(self.data)):
assert type(self.data[j]) == type(i.data[j]), \
- "type mismatch in IntegerData %s %s" % \
+ "type mismatch in FUBaseData %s %s" % \
(repr(self.data[j]), repr(i.data[j]))
eqs.append(self.data[j].eq(i.data[j]))
+ if hasattr(self, "exception"):
+ eqs.append(self.exception.eq(i.exception))
return eqs
def ports(self):