whoops was still copying output over in CommonOutputStage

[soc.git] / src / soc / fu / pipe_data.py

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
index 1faf2a6f7322603bf27a4b406db62c6031df4994..abee2df9a9c91050f7978ebac50b9b4acbd5e94e 100644 (file)
--- a/src/soc/fu/pipe_data.py
+++ b/src/soc/fu/pipe_data.py
@@ -1,17 +1,28 @@
 from nmutil.concurrentunit import PipeContext
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from nmigen import Signal
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
 from soc.fu.regspec import get_regspec_bitwidth
 
 
-class IntegerData:
+class FUBaseData:
+    """FUBaseData: base class for all pipeline data structures
 
-    def __init__(self, pspec, output):
+    see README.md for explanation of parameters and purpose.
+
+    note the mode parameter - output.  XXXInputData specs must
+    have this set to "False", and XXXOutputData specs (and anything
+    that creates intermediary outputs which propagate through a
+    pipeline *to* output) must have it set to "True".
+    """
+
+    def __init__(self, pspec, output, exc_kls=None):
         self.ctx = PipeContext(pspec) # context for ReservationStation usage
         self.muxid = self.ctx.muxid
         self.data = []
         self.is_output = output
+        # take regspec and create data attributes (in or out)
+        # TODO: use widspec to create reduced bit mapping.
         for i, (regfile, regname, widspec) in enumerate(self.regspec):
             wid = get_regspec_bitwidth([self.regspec], 0, i)
             if output:
@@ -20,10 +31,16 @@ class IntegerData:
                 sig = Signal(wid, name=regname, reset_less=True)
             setattr(self, regname, sig)
             self.data.append(sig)
+        # optional exception type
+        if exc_kls is not None:
+            name = "exc_o" if output else "exc_i"
+            self.exception = exc_kls(name=name)
 
     def __iter__(self):
         yield from self.ctx
         yield from self.data
+        if hasattr(self, "exception"):
+            yield from self.exception.ports()
 
     def eq(self, i):
         eqs = [self.ctx.eq(i.ctx)]
@@ -32,9 +49,11 @@ class IntegerData:
                    (repr(self), repr(i), repr(self.data), repr(i.data))
         for j in range(len(self.data)):
             assert type(self.data[j]) == type(i.data[j]), \
-                   "type mismatch in IntegerData %s %s" % \
+                   "type mismatch in FUBaseData %s %s" % \
                    (repr(self.data[j]), repr(i.data[j]))
             eqs.append(self.data[j].eq(i.data[j]))
+        if hasattr(self, "exception"):
+            eqs.append(self.exception.eq(i.exception))
         return eqs
 
     def ports(self):
@@ -52,9 +71,12 @@ def get_rec_width(rec):
 
 
 class CommonPipeSpec:
+    """CommonPipeSpec: base class for all pipeline specifications
+    see README.md for explanation of members.
+    """
     def __init__(self, id_wid):
         self.pipekls = SimpleHandshakeRedir
         self.id_wid = id_wid
-        self.opkls = lambda _: self.opsubsetkls(name="op")
+        self.opkls = lambda _: self.opsubsetkls()
         self.op_wid = get_rec_width(self.opkls(None)) # hmm..
         self.stage = None