-from nmigen import Signal, Const
-from nmutil.dynamicpipe import SimpleHandshakeRedir
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from ieee754.fpcommon.getop import FPPipeContext
+from soc.fu.shift_rot.sr_input_record import CompSROpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.logical.pipe_data import LogicalOutputData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.alu.pipe_data import ALUOutputData
class ShiftRotInputData(IntegerData):
- regspec = [('INT', 'a', '0:63'),
- ('INT', 'rb', '0:63'),
- ('INT', 'rs', '0:63'),
- ('XER', 'xer_ca', '34,45')]
+ regspec = [('INT', 'ra', '0:63'), # RA
+ ('INT', 'rb', '0:63'), # RB
+ ('INT', 'rc', '0:63'), # RS
+ ('XER', 'xer_so', '32'), # XER bit 32: SO
+ ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
def __init__(self, pspec):
- super().__init__(pspec)
- self.a = Signal(64, reset_less=True) # RA
- self.rb = Signal(64, reset_less=True) # RB/immediate
- self.rs = Signal(64, reset_less=True) # RS
- self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
-
- def __iter__(self):
- yield from super().__iter__()
- yield self.a
- yield self.rb
- yield self.rs
- yield self.xer_ca
-
- def eq(self, i):
- lst = super().eq(i)
- return lst + [self.rs.eq(i.rs), self.a.eq(i.a),
- self.rb.eq(i.rb),
- self.xer_ca.eq(i.xer_ca) ]
-
-
-# TODO: replace CompALUOpSubset with CompShiftRotOpSubset
+ super().__init__(pspec, False)
+ # convenience
+ self.a, self.b, self.rs = self.ra, self.rb, self.rc
+
+
+# input to shiftrot final stage (common output)
+class ShiftRotOutputData(IntegerData):
+ regspec = [('INT', 'o', '0:63'), # RT
+ ('CR', 'cr_a', '0:3'),
+ ('XER', 'xer_so', '32'), # bit0: so
+ ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+ ]
+ def __init__(self, pspec):
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+
+# output from shiftrot final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class ShiftRotOutputDataFinal(IntegerData):
+ regspec = [('INT', 'o', '0:63'), # RT
+ ('CR', 'cr_a', '0:3'),
+ ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+ ]
+ def __init__(self, pspec):
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+
class ShiftRotPipeSpec(CommonPipeSpec):
- regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
- opsubsetkls = CompALUOpSubset
+ regspec = (ShiftRotInputData.regspec, ShiftRotOutputDataFinal.regspec)
+ opsubsetkls = CompSROpSubset