TODO on RA immediate-zero mode

[soc.git] / src / soc / fu / test / common.py

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index e373a70887daab4468b540bb34a4c74acccb21b8..9a97652ef6125aef388dcc1add53cb9d586aab2a 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -1,3 +1,6 @@
+from soc.decoder.power_enums import XER_bits
+
+
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
                        msr=0):
@@ -19,7 +22,21 @@ class TestCase:
 
 class ALUHelpers:
 
+    def get_sim_int_ra(res, sim, dec2):
+        # TODO: immediate RA zero
+        reg1_ok = yield dec2.e.read_reg1.ok
+        if reg1_ok:
+            data1 = yield dec2.e.read_reg1.data
+            res['ra'] = sim.gpr(data1).value
+
+    def get_sim_int_rb(res, sim, dec2):
+        reg2_ok = yield dec2.e.read_reg2.ok
+        if reg2_ok:
+            data = yield dec2.e.read_reg2.data
+            res['rb'] = sim.gpr(data).value
+
     def set_int_ra(alu, dec2, inp):
+        # TODO: immediate RA zero.
         if 'ra' in inp:
             yield alu.p.data_i.ra.eq(inp['ra'])
         else:
@@ -83,9 +100,97 @@ class ALUHelpers:
             yield alu.p.data_i.full_cr.eq(0)
 
     def get_int_o(res, alu, dec2):
-        out_reg_valid = yield pdecode2.e.write_reg.ok
+        out_reg_valid = yield dec2.e.write_reg.ok
         if out_reg_valid:
             res['o'] = yield alu.n.data_o.o.data 
 
-    def check_int_o(dut, alu, sim, dec2):
-        pass
+    def get_cr_a(res, alu, dec2):
+        cridx_ok = yield dec2.e.write_cr.ok
+        if cridx_ok:
+            res['cr_a'] = yield alu.n.data_o.cr0.data
+
+    def get_xer_so(res, alu, dec2):
+        oe = yield dec2.e.oe.oe
+        oe_ok = yield dec2.e.oe.ok
+        if oe and oe_ok:
+            res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
+
+    def get_xer_ov(res, alu, dec2):
+        oe = yield dec2.e.oe.oe
+        oe_ok = yield dec2.e.oe.ok
+        if oe and oe_ok:
+            res['xer_ov'] = yield alu.n.data_o.xer_ov.data
+
+    def get_xer_ca(res, alu, dec2):
+        cry_out = yield dec2.e.output_carry
+        if cry_out:
+            res['xer_ca'] = yield alu.n.data_o.xer_ca.data
+
+    def get_sim_int_o(res, sim, dec2):
+        out_reg_valid = yield dec2.e.write_reg.ok
+        if out_reg_valid:
+            write_reg_idx = yield dec2.e.write_reg.data
+            res['o'] = sim.gpr(write_reg_idx).value
+
+    def get_sim_cr_a(res, sim, dec2):
+        cridx_ok = yield dec2.e.write_cr.ok
+        if cridx_ok:
+            cridx = yield dec2.e.write_cr.data
+            res['cr_a'] = sim.crl[cridx].get_range().value
+
+    def get_sim_xer_ca(res, sim, dec2):
+        cry_out = yield dec2.e.output_carry
+        if cry_out:
+            expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+            expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+            res['xer_ca'] = expected_carry | (expected_carry32 << 1)
+
+    def get_sim_xer_ov(res, sim, dec2):
+        oe = yield dec2.e.oe.oe
+        oe_ok = yield dec2.e.oe.ok
+        if oe and oe_ok:
+            expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+            expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+            res['xer_ov'] = expected_ov | (expected_ov32 << 1)
+
+    def get_sim_xer_so(res, sim, dec2):
+        oe = yield dec2.e.oe.oe
+        oe_ok = yield dec2.e.oe.ok
+        if oe and oe_ok:
+            res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+
+    def check_int_o(dut, res, sim_o, msg):
+        if 'o' in res:
+            expected = sim_o['o']
+            alu_out = res['o']
+            print(f"expected {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
+    def check_cr_a(dut, res, sim_o, msg):
+        if 'cr_a' in res:
+            cr_expected = sim_o['cr_a']
+            cr_actual = res['cr_a']
+            print ("CR", cr_expected, cr_actual)
+            dut.assertEqual(cr_expected, cr_actual, msg)
+
+    def check_xer_ca(dut, res, sim_o, msg):
+        if 'xer_ca' in res:
+            ca_expected = sim_o['xer_ca']
+            ca_actual = res['xer_ca']
+            print ("CA", ca_expected, ca_actual)
+            dut.assertEqual(ca_expected, ca_actual, msg)
+
+    def check_xer_ov(dut, res, sim_o, msg):
+        if 'xer_ov' in res:
+            ov_expected = sim_o['xer_ov']
+            ov_actual = res['xer_ov']
+            print ("OV", ov_expected, ov_actual)
+            dut.assertEqual(ov_expected, ov_actual, msg)
+
+    def check_xer_so(dut, res, sim_o, msg):
+        if 'xer_so' in res:
+            so_expected = sim_o['xer_so']
+            so_actual = res['xer_so']
+            print ("SO", so_expected, so_actual)
+            dut.assertEqual(so_expected, so_actual, msg)
+