reduce sdram pins to smaller address and only 1 cs_n

[soc.git] / src / soc / litex / sim.py

diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py
index 24845ec7cdfe37f81d9a641d1f453abcdb2ef414..a993535370ae67c31472b4f2f28feaba7fd70015 100644 (file)
--- a/src/soc/litex/sim.py
+++ b/src/soc/litex/sim.py
@@ -4,19 +4,20 @@
 # This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
 # License: BSD
 
+import os
 import argparse
 
-from migen import *
-
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
+from litex.build.io import CRG
 from litex.build.sim.config import SimConfig
 
 from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.soc_core import SoCCore
 from litex.soc.integration.common import get_mem_data
+from litex.soc.integration.builder import Builder
 
-from litedram.modules import MT41K128M16
+from litedram.modules import IS42S16160, MT41K128M16
 from litedram.phy.model import SDRAMPHYModel
 from litedram.core.controller import ControllerSettings
 
@@ -64,34 +65,43 @@ class SoCSMP(SoCCore):
 
         # SoCCore --------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            cpu_type                 = "libre-soc",
-            cpu_variant=cpu_variant,
-            cpu_cls=LibreSOC,
+            cpu_type                 = "microwatt", # XXX use microwatt
+            cpu_variant              = cpu_variant,
+            cpu_cls                  = LibreSOC,
+            bus_data_width           = 32, # XXX TODO 64 bit wishbone data bus
             uart_name                = "sim",
             integrated_rom_size      = 0x8000,
             integrated_main_ram_size = 0x00000000)
+
         self.platform.name = "sim"
         self.add_constant("SIM")
 
+        # CRG -------------------------------------------------------
+        self.submodules.crg = CRG(platform.request("sys_clk"))
+
         # SDRAM ----------------------------------------------------------
-        phy_settings = get_sdram_phy_settings(
-            memtype    = "DDR3",
-            data_width = 16,
-            clk_freq   = 100e6)
-        self.submodules.sdrphy = SDRAMPHYModel(
-            module    = MT41K128M16(100e6, "1:4"),
-            settings  = phy_settings,
-            clk_freq  = 100e6,
-            init      = sdram_init)
-        self.add_sdram("sdram",
-            phy                     = self.sdrphy,
-            module                  = MT41K128M16(100e6, "1:4"),
-            origin                  = self.mem_map["main_ram"],
-            controller_settings     = ControllerSettings(
-                cmd_buffer_buffered = False,
-                with_auto_precharge = True
+        if False:
+            phy_settings = get_sdram_phy_settings(
+                #memtype    = "DDR3",
+                memtype    = "SDR",
+                data_width = 16,
+                clk_freq   = 100e6)
+            self.submodules.sdrphy = SDRAMPHYModel(
+                #module    = MT41K128M16(100e6, "1:4"),
+                module                  = IS42S16160(100e6, "1:4"),
+                settings  = phy_settings,
+                clk_freq  = 100e6,
+                init      = sdram_init)
+            self.add_sdram("sdram",
+                phy                     = self.sdrphy,
+                #module                  = MT41K128M16(100e6, "1:4"),
+                module                  = IS42S16160(100e6, "1:4"),
+                origin                  = self.mem_map["main_ram"],
+                #controller_settings     = ControllerSettings(
+                #    cmd_buffer_buffered = False,
+                #    with_auto_precharge = True
+                #)
             )
-        )
         if init_memories:
             addr = 0x40f00000
             self.add_constant("MEMTEST_BUS_SIZE",  0) # Skip test if memory is
@@ -99,15 +109,15 @@ class SoCSMP(SoCCore):
             self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content.
             self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin
         else:
-            self.add_constant("MEMTEST_BUS_SIZE",  4096)
-            self.add_constant("MEMTEST_ADDR_SIZE", 4096)
-            self.add_constant("MEMTEST_DATA_SIZE", 4096)
+            self.add_constant("MEMTEST_BUS_SIZE",  4096//64)
+            self.add_constant("MEMTEST_ADDR_SIZE", 4096//256)
+            self.add_constant("MEMTEST_DATA_SIZE", 4096//32)
 
         # SDCard -----------------------------------------------------
         if with_sdcard:
             self.add_sdcard("sdcard", use_emulator=True)
 
-# Build --------------------------------------------------------------------------------------------
+# Build -----------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(
@@ -132,19 +142,19 @@ def main():
     sim_config.add_module("serial2console", "serial")
 
     for i in range(2):
-        to_run = (i != 0) # first build, then run
+        to_run = (i != 0) # first build (i=0), then run (i=1)
         soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run,
                      args.with_sdcard)
         builder = Builder(soc,
             compile_gateware = to_run,
             csr_json         = "build/sim/csr.json")
         builder.build(sim_config=sim_config,
-            run         = i!=0,
+            run         = to_run,
             opt_level   = args.opt_level,
             trace       = args.trace,
             trace_start = int(args.trace_start),
             trace_end   = int(args.trace_end),
-            trace_fst   = 1)
+            trace_fst   = 0)
         os.chdir("../")
         #if not to_run:
         #  os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME