first test of down-converted load/store from 64 to 32 bit

[soc.git] / src / soc / minerva / units / loadstore.py

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index de3246e90515548354e5de8b388c4b62b73bb0be..3526709de5e179f334376d51f15230e125c50d8b 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -19,7 +19,7 @@ class LoadStoreUnitInterface:
         print(self.dbus.sel.shape())
         if isinstance(pspec.wb_data_wid, int):
             pspecslave = deepcopy(pspec)
-            pspecslave.data_wid = pspec.wb_data_wid
+            pspecslave.reg_wid = pspec.wb_data_wid
             self.slavebus = Record(make_wb_layout(pspecslave))
             self.cvt = WishboneDownConvert(self.dbus, self.slavebus)
         self.mask_wid = mask_wid = pspec.mask_wid
@@ -88,7 +88,7 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         m = Module()
 
         if hasattr(self, "cvt"):
-            m.submodules.cvt = cvt
+            m.submodules.cvt = self.cvt
 
         with m.If(self.dbus.cyc):
             with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid_i):