port minerva cache fixes

[soc.git] / src / soc / minerva / units / loadstore.py

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index a4d76d1972359d5edcbfbe4c720febcb5eb21d54..499daf216857f601e983bad8ca1b5242bcdddde8 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -257,9 +257,9 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
                 self.m_busy_o.eq(0),
                 self.m_ld_data_o.eq(0)
             ]
-        with m.Elif(m_dcache_select):
+        with m.Elif(self.m_load & m_dcache_select):
             m.d.comb += [
-                self.m_busy_o.eq(dcache.s2_re & dcache.s2_miss),
+                self.m_busy_o.eq(dcache.s2_miss),
                 self.m_ld_data_o.eq(dcache.s2_rdata)
             ]
         with m.Else():