# TODO
-from soc.regfile import RegFile, RegFileArray
+from soc.regfile.regfile import RegFile, RegFileArray
from soc.regfile.virtual_port import VirtualRegPort
from soc.decoder.power_enums import SPR
"""IntRegs
* QTY 32of 64-bit registers
- * 3R1W
+ * 3R2W
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
"""
def __init__(self):
super().__init__(64, 32)
- self.w_ports = [self.write_port("dest")]
- self.r_ports = [self.write_port("src1"),
- self.write_port("src2"),
- self.write_port("src3")]
+ self.w_ports = [self.write_port("dest1"),
+ self.write_port("dest2")] # for now (LD/ST update)
+ self.r_ports = [self.read_port("src1"),
+ self.read_port("src2"),
+ self.read_port("src3")]
+
+
+# Fast SPRs Regfile
+class FastRegs(RegFileArray):
+ """FastRegs
+
+ FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2
+
+ * QTY 8of 64-bit registers
+ * 3R2W
+ * Array-based unary-indexed (not binary-indexed)
+ * write-through capability (read on same cycle as write)
+ """
+ PC = 0
+ MSR = 1
+ CTR = 2
+ LR = 3
+ TAR = 4
+ SRR1 = 5
+ SRR2 = 6
+ def __init__(self):
+ super().__init__(64, 8)
+ self.w_ports = [self.write_port("dest1"),
+ self.write_port("dest2")]
+ self.r_ports = [self.read_port("src1"),
+ self.read_port("src2"),
+ self.read_port("src3")]
# CR Regfile
self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
self.write_port("dest")] # 4-bit wide, unary-indexed
self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
- self.write_port("src1"),
- self.write_port("src2"),
- self.write_port("src3")]
+ self.read_port("src1"),
+ self.read_port("src2"),
+ self.read_port("src3")]
# XER Regfile
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
"""
+ SO=0 # this is actually 2-bit but we ignore 1 bit of it
+ CA=1 # CA and CA32
+ OV=2 # OV and OV32
def __init__(self):
super().__init__(6, 2)
self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
self.write_port("dest1"),
- self.write_port("dest2",
+ self.write_port("dest2"),
self.write_port("dest3")]
self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
- self.write_port("src1"),
- self.write_port("src2"),
- self.write_port("src3")]
+ self.read_port("src1"),
+ self.read_port("src2"),
+ self.read_port("src3")]
# SPR Regfile
def __init__(self):
n_sprs = len(SPR)
super().__init__(64, n_sprs)
- self.w_ports = [self.write_port("dest")]
- self.r_ports = [self.write_port("src")]
+ self.w_ports = [self.write_port(name="dest")]
+ self.r_ports = [self.read_port("src")]
+
+
+# class containing all regfiles: int, cr, xer, fast, spr
+class RegFiles:
+ def __init__(self):
+ self.rf = {}
+ for (name, kls) in [('int', IntRegs),
+ ('cr', CRRegs),
+ ('xer', XERRegs),
+ ('fasr', FastRegs),
+ ('spr', SPRRegs),]:
+ rf = self.rf[name] = kls()
+ setattr(self, name, rf)
+
+ def elaborate_into(self, m, platform):
+ for (name, rf) in self.rf.items():
+ setattr(m.submodules, name, rf)
+ return m
+