start putting a non-production core together,

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index d6f3a8dd79930d1286c72a42328363d9b9b8e9f3..4dfb522a2ebdaa19b77fbe57c3fc7133bdc182c1 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -3,22 +3,24 @@
 
 Defines the following register files:
 
-    * INT regfile
-    * SPR regfile
-    * CR regfile
-    * XER regfile
-    * FAST regfile
+    * INT regfile   - 32x 64-bit
+    * SPR regfile   - 110x 64-bit
+    * CR regfile    - CR0-7
+    * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
+    * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
 
 Links:
 
 * https://bugs.libre-soc.org/show_bug.cgi?id=345
+* https://bugs.libre-soc.org/show_bug.cgi?id=351
 * https://libre-soc.org/3d_gpu/architecture/regfile/
 * https://libre-soc.org/openpower/isatables/sprs.csv
 """
 
 # TODO
 
-from soc.regfile import RegFile, RegFileArray
+from soc.regfile.regfile import RegFile, RegFileArray
+from soc.regfile.virtual_port import VirtualRegPort
 from soc.decoder.power_enums import SPR
 
 
@@ -27,33 +29,87 @@ class IntRegs(RegFileArray):
     """IntRegs
 
     * QTY 32of 64-bit registers
-    * 3R1W
+    * 3R2W
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
     """
     def __init__(self):
         super().__init__(64, 32)
-        self.w_ports = [self.write_port("dest")]
-        self.r_ports = [self.write_port("src1"),
-                        self.write_port("src2"),
-                        self.write_port("src3")]
+        self.w_ports = [self.write_port("dest1"),
+                        self.write_port("dest2")] # for now (LD/ST update)
+        self.r_ports = [self.read_port("src1"),
+                        self.read_port("src2"),
+                        self.read_port("src3")]
+
+
+# Fast SPRs Regfile
+class FastRegs(RegFileArray):
+    """FastRegs
+
+    FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
+
+    * QTY 8of 64-bit registers
+    * 3R2W
+    * Array-based unary-indexed (not binary-indexed)
+    * write-through capability (read on same cycle as write)
+    """
+    PC = 0
+    MSR = 1
+    CTR = 2
+    LR = 3
+    TAR = 4
+    SRR1 = 5
+    SRR2 = 6
+    def __init__(self):
+        super().__init__(64, 8)
+        self.w_ports = [self.write_port("dest1"),
+                        self.write_port("dest2")]
+        self.r_ports = [self.read_port("src1"),
+                        self.read_port("src2"),
+                        self.read_port("src3")]
 
 
 # CR Regfile
-class CRRegs(RegFileArray):
+class CRRegs(VirtualRegPort):
     """Condition Code Registers (CR0-7)
 
     * QTY 8of 8-bit registers
-    * 8R8W (!) with additional 1R1W for the "full" width
+    * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
+    * Array-based unary-indexed (not binary-indexed)
+    * write-through capability (read on same cycle as write)
+    """
+    def __init__(self):
+        super().__init__(32, 8)
+        self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
+                        self.write_port("dest")] # 4-bit wide, unary-indexed
+        self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
+                        self.read_port("src1"),
+                        self.read_port("src2"),
+                        self.read_port("src3")]
+
+
+# XER Regfile
+class XERRegs(VirtualRegPort):
+    """XER Registers (SO, CA/CA32, OV/OV32)
+
+    * QTY 3of 2-bit registers
+    * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
     """
+    SO=0 # this is actually 2-bit but we ignore 1 bit of it
+    CA=1 # CA and CA32
+    OV=2 # OV and OV32
     def __init__(self):
-        super().__init__(4, 8)
-        self.w_ports = [self.write_port("dest")]
-        self.r_ports = [self.write_port("src1"),
-                        self.write_port("src2"),
-                        self.write_port("src3")]
+        super().__init__(6, 2)
+        self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
+                        self.write_port("dest1"),
+                        self.write_port("dest2"),
+                        self.write_port("dest3")]
+        self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
+                        self.read_port("src1"),
+                        self.read_port("src2"),
+                        self.read_port("src3")]
 
 
 # SPR Regfile
@@ -68,5 +124,24 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = [self.write_port("dest")]
-        self.r_ports = [self.write_port("src")]
+        self.w_ports = [self.write_port(name="dest")]
+        self.r_ports = [self.read_port("src")]
+
+
+# class containing all regfiles: int, cr, xer, fast, spr
+class RegFiles:
+    def __init__(self):
+        self.rf = {}
+        for (name, kls) in [('int', IntRegs),
+                            ('cr', CRRegs),
+                            ('xer', XERRegs),
+                            ('fasr', FastRegs),
+                            ('spr', SPRRegs),]:
+            rf = self.rf[name] = kls()
+            setattr(self, name, rf)
+
+    def elaborate_into(self, m, platform):
+        for (name, rf) in self.rf.items():
+            setattr(m.submodules, name, rf)
+        return m
+