start putting a non-production core together,

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index dc92f0c4973d6ed758baf118acb5bb6b6ac52b48..4dfb522a2ebdaa19b77fbe57c3fc7133bdc182c1 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -124,15 +124,24 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = [self.write_port("dest")]
+        self.w_ports = [self.write_port(name="dest")]
         self.r_ports = [self.read_port("src")]
 
 
+# class containing all regfiles: int, cr, xer, fast, spr
 class RegFiles:
     def __init__(self):
-        self.int = IntRegs()
-        self.cr = CRRegs()
-        self.xer = XERRegs()
-        self.fasr = FastRegs()
-        self.spr = SPRRegs()
+        self.rf = {}
+        for (name, kls) in [('int', IntRegs),
+                            ('cr', CRRegs),
+                            ('xer', XERRegs),
+                            ('fasr', FastRegs),
+                            ('spr', SPRRegs),]:
+            rf = self.rf[name] = kls()
+            setattr(self, name, rf)
+
+    def elaborate_into(self, m, platform):
+        for (name, rf) in self.rf.items():
+            setattr(m.submodules, name, rf)
+        return m