Fix indentation of regfile/formal/proof_regfile.py

[soc.git] / src / soc / regfile / virtual_port.py

diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py
index 152fb4cd53d1a8fd6c0461bea0272ee0a705f959..322efe8e73588a7d6dd4f2761572957086781111 100644 (file)
--- a/src/soc/regfile/virtual_port.py
+++ b/src/soc/regfile/virtual_port.py
@@ -92,9 +92,10 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp):
     yield rp2.ren.eq(0)
     data1 = yield rp1.data_o
     print (data1)
+    assert data1 == 6, data1
     data2 = yield rp2.data_o
     print (data2)
-    assert data1 == 6
+    assert data2 == 2, data2
     yield
     data = yield rp1.data_o
     print (data)