from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
from nmigen.cli import rtlil
-from soc.decoder.power_decoder2 import PowerDecodeSubset
-from soc.decoder.power_regspec_map import regspec_decode_read
-from soc.decoder.power_regspec_map import regspec_decode_write
+from openpower.decoder.power_decoder2 import PowerDecodeSubset
+from openpower.decoder.power_regspec_map import regspec_decode_read
+from openpower.decoder.power_regspec_map import regspec_decode_write
+from openpower.sv.svp64 import SVP64Rec
from nmutil.picker import PriorityPicker
from nmutil.util import treereduce
from soc.fu.compunits.compunits import AllFunctionUnits
from soc.regfile.regfiles import RegFiles
-from soc.decoder.decode2execute1 import Decode2ToExecute1Type
-from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
-from soc.decoder.power_decoder2 import get_rdflags
-from soc.decoder.decode2execute1 import Data
+from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
+from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
+from openpower.decoder.power_decoder2 import get_rdflags
+from openpower.decoder.decode2execute1 import Data
from soc.experiment.l0_cache import TstL0CacheBuffer # test only
from soc.config.test.test_loadstore import TestMemPspec
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from soc.config.state import CoreState
import operator
# helper function for reducing a list of signals down to a parallel
# ORed single signal.
-def ortreereduce(tree, attr="data_o"):
+def ortreereduce(tree, attr="o_data"):
return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
def __init__(self, pspec):
self.pspec = pspec
+ # test is SVP64 is to be enabled
+ self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
+
+ # test to see if regfile ports should be reduced
+ self.regreduce_en = (hasattr(pspec, "regreduce") and
+ (pspec.regreduce == True))
+
# single LD/ST funnel for memory access
- self.l0 = TstL0CacheBuffer(pspec, n_units=1)
- pi = self.l0.l0.dports[0]
+ self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
+ pi = l0.l0.dports[0]
# function units (only one each)
# only include mmu if enabled in pspec
self.fus = AllFunctionUnits(pspec, pilist=[pi])
+ # link LoadStore1 into MMU
+ mmu = self.fus.get_fu('mmu0')
+ print ("core pspec", pspec.ldst_ifacetype)
+ print ("core mmu", mmu)
+ print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
+ if mmu is not None:
+ mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
+
# register files (yes plural)
- self.regs = RegFiles()
+ self.regs = RegFiles(pspec)
# instruction decoder - needs a Trap-capable Record (captures EINT etc.)
- self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand)
+ self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
+ regreduce_en=self.regreduce_en)
+ # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
+ self.sv_a_nz = Signal()
+
+ # state and raw instruction (and SVP64 ReMap fields)
self.state = CoreState("core")
self.raw_insn_i = Signal(32) # raw instruction
- self.bigendian_i = Signal() # bigendian
+ self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
+ if self.svp64_en:
+ self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
+ self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
+ self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
+ self.sv_pred_sm = Signal() # TODO: SIMD width
+ self.sv_pred_dm = Signal() # TODO: SIMD width
# issue/valid/busy signalling
self.ivalid_i = Signal(reset_less=True) # instruction is valid
self.busy_o = Signal(name="corebusy_o", reset_less=True)
# start/stop and terminated signalling
- self.core_stopped_i = Signal(reset_less=True)
self.core_terminate_o = Signal(reset=0) # indicates stopped
# create per-FU instruction decoders (subsetted)
fnunit = fu.fnunit.value
opkls = fu.opsubsetkls
if f_name == 'TRAP':
+ # TRAP decoder is the *main* decoder
self.trapunit = funame
continue
self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
final=True,
- state=self.state)
+ state=self.state,
+ svp64_en=self.svp64_en,
+ regreduce_en=self.regreduce_en)
self.des[funame] = self.decoders[funame].do
+ if "mmu0" in self.decoders:
+ self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
+
def elaborate(self, platform):
m = Module()
# for testing purposes, to cut down on build time in coriolis2
setattr(m.submodules, "dec_%s" % v.fn_name, v)
comb += v.dec.raw_opcode_in.eq(self.raw_insn_i)
comb += v.dec.bigendian.eq(self.bigendian_i)
+ # sigh due to SVP64 RA_OR_ZERO detection connect these too
+ comb += v.sv_a_nz.eq(self.sv_a_nz)
+ if self.svp64_en:
+ comb += v.pred_sm.eq(self.sv_pred_sm)
+ comb += v.pred_dm.eq(self.sv_pred_dm)
+ if k != self.trapunit:
+ comb += v.sv_rm.eq(self.sv_rm) # pass through SVP64 ReMap
+ comb += v.is_svp64_mode.eq(self.is_svp64_mode)
+ # only the LDST PowerDecodeSubset *actually* needs to
+ # know to use the alternative decoder. this is all
+ # a terrible hack
+ if k.lower().startswith("ldst"):
+ comb += v.use_svp64_ldst_dec.eq(self.use_svp64_ldst_dec)
# ssh, cheat: trap uses the main decoder because of the rewriting
self.des[self.trapunit] = self.e.do
src = fu.src_i[idx]
print("reg connect widths",
regfile, regname, pi, funame,
- src.shape(), rport.data_o.shape())
+ src.shape(), rport.o_data.shape())
# all FUs connect to same port
- comb += src.eq(rport.data_o)
+ comb += src.eq(rport.o_data)
# or-reduce the muxed read signals
if rfile.unary:
# argh. an experiment to merge RA and RB in the INT regfile
# (we have too many read/write ports)
- #if regfile == 'INT':
- #fuspecs['rabc'] = [fuspecs.pop('rb')]
- #fuspecs['rabc'].append(fuspecs.pop('rc'))
- #fuspecs['rabc'].append(fuspecs.pop('ra'))
- #if regfile == 'FAST':
- # fuspecs['fast1'] = [fuspecs.pop('fast1')]
- # if 'fast2' in fuspecs:
- # fuspecs['fast1'].append(fuspecs.pop('fast2'))
+ if self.regreduce_en:
+ if regfile == 'INT':
+ fuspecs['rabc'] = [fuspecs.pop('rb')]
+ fuspecs['rabc'].append(fuspecs.pop('rc'))
+ fuspecs['rabc'].append(fuspecs.pop('ra'))
+ if regfile == 'FAST':
+ fuspecs['fast1'] = [fuspecs.pop('fast1')]
+ if 'fast2' in fuspecs:
+ fuspecs['fast1'].append(fuspecs.pop('fast2'))
+ if 'fast3' in fuspecs:
+ fuspecs['fast1'].append(fuspecs.pop('fast3'))
# for each named regfile port, connect up all FUs to that port
for (regname, fspec) in sort_fuspecs(fuspecs):
# connect regfile port to input
print("reg connect widths",
regfile, regname, pi, funame,
- dest.shape(), wport.data_i.shape())
+ dest.shape(), wport.i_data.shape())
wsigs.append(fu_dest_latch)
# here is where we create the Write Broadcast Bus. simple, eh?
- comb += wport.data_i.eq(ortreereduce_sig(wsigs))
+ comb += wport.i_data.eq(ortreereduce_sig(wsigs))
if rfile.unary:
# for unary-addressed
comb += wport.wen.eq(ortreereduce_sig(wens))
fuspecs = byregfiles_wrspec[regfile]
wrpickers[regfile] = {}
- # argh, more port-merging
- if regfile == 'INT':
- fuspecs['o'] = [fuspecs.pop('o')]
- fuspecs['o'].append(fuspecs.pop('o1'))
- if regfile == 'FAST':
- fuspecs['fast1'] = [fuspecs.pop('fast1')]
- if 'fast2' in fuspecs:
- fuspecs['fast1'].append(fuspecs.pop('fast2'))
+ if self.regreduce_en:
+ # argh, more port-merging
+ if regfile == 'INT':
+ fuspecs['o'] = [fuspecs.pop('o')]
+ fuspecs['o'].append(fuspecs.pop('o1'))
+ if regfile == 'FAST':
+ fuspecs['fast1'] = [fuspecs.pop('fast1')]
+ if 'fast2' in fuspecs:
+ fuspecs['fast1'].append(fuspecs.pop('fast2'))
+ if 'fast3' in fuspecs:
+ fuspecs['fast1'].append(fuspecs.pop('fast3'))
for (regname, fspec) in sort_fuspecs(fuspecs):
self.connect_wrport(m, fu_bitdict, wrpickers,
projects / soc.git / blobdiff