add a new run_hdl parameter to TestRunner

[soc.git] / src / soc / simple / core.py

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index e9eb1a189a29c6036868bd049fe75b6b3f9ae405..65643115173926ed7a7499c0c75ad60e45116275 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -48,7 +48,7 @@ from nmutil.util import rising_edge
 
 # helper function for reducing a list of signals down to a parallel
 # ORed single signal.
-def ortreereduce(tree, attr="data_o"):
+def ortreereduce(tree, attr="o_data"):
     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
 
 
@@ -117,7 +117,7 @@ class NonProductionCore(Elaboratable):
             self.sv_pred_dm = Signal() # TODO: SIMD width
 
         # issue/valid/busy signalling
-        self.ii_valid = Signal(reset_less=True) # instruction is valid
+        self.ivalid_i = Signal(reset_less=True) # instruction is valid
         self.issue_i = Signal(reset_less=True)
         self.busy_o = Signal(name="corebusy_o", reset_less=True)
 
@@ -226,7 +226,7 @@ class NonProductionCore(Elaboratable):
             sync += counter.eq(counter - 1)
             comb += self.busy_o.eq(1)
 
-        with m.If(self.ii_valid): # run only when valid
+        with m.If(self.ivalid_i): # run only when valid
             with m.Switch(self.e.do.insn_type):
                 # check for ATTN: halt if true
                 with m.Case(MicrOp.OP_ATTN):
@@ -338,9 +338,9 @@ class NonProductionCore(Elaboratable):
                     src = fu.src_i[idx]
                     print("reg connect widths",
                           regfile, regname, pi, funame,
-                          src.shape(), rport.data_o.shape())
+                          src.shape(), rport.o_data.shape())
                     # all FUs connect to same port
-                    comb += src.eq(rport.data_o)
+                    comb += src.eq(rport.o_data)
 
         # or-reduce the muxed read signals
         if rfile.unary:
@@ -466,11 +466,11 @@ class NonProductionCore(Elaboratable):
                 # connect regfile port to input
                 print("reg connect widths",
                       regfile, regname, pi, funame,
-                      dest.shape(), wport.data_i.shape())
+                      dest.shape(), wport.i_data.shape())
                 wsigs.append(fu_dest_latch)
 
         # here is where we create the Write Broadcast Bus. simple, eh?
-        comb += wport.data_i.eq(ortreereduce_sig(wsigs))
+        comb += wport.i_data.eq(ortreereduce_sig(wsigs))
         if rfile.unary:
             # for unary-addressed
             comb += wport.wen.eq(ortreereduce_sig(wens))