whoops MFSPR DEC/TB was reading from FastRegs not StateRegs

[soc.git] / src / soc / simple / core.py

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index d9c398b4143cddad422465a8bba422070d3510c4..6c2d7388a0dc74afd47c5af19c7d8f8a9c2896a8 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -523,7 +523,8 @@ class NonProductionCore(ControlBase):
                 # spot MTSPR, spot that DEC/TB is what is to be updated.
                 # a job for PowerDecoder2, there
                 if funame.lower().startswith('spr'):
-                    with m.If(fu.busy_o):
+                    with m.If(fu.busy_o #& fu.oper_i.insn_type == OP_MTSPR
+                        ):
                         comb += self.pause_dec_tb.eq(1)
 
         # return both the function unit "enable" dict as well as the "busy".