# 3 bits, unary: return the port
if regfile == 'XER':
return port
- # 3 bits, unary: return the port
- if regfile == 'SVSTATE':
+ # 5 bits, unary: return the port
+ if regfile == 'STATE':
return port
# 9 bits (9 entries), might be unary already
if regfile == 'FAST':
# urr store I-Cache in core so it is easier to get at
self.icache = lsi.icache
+ # alternative reset values for STATE regs. these probably shouldn't
+ # be set, here, instead have them done by Issuer. which they are.
+ # as well. because core.state overrides them. sigh.
self.msr_at_reset = 0x0
+ self.pc_at_reset = 0x0
if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int):
self.msr_at_reset = pspec.msr_reset
- state_resets = [0x0, # PC at reset
+ if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int):
+ self.pc_at_reset = pspec.pc_reset
+ state_resets = [self.pc_at_reset, # PC at reset
self.msr_at_reset, # MSR at reset
0x0, # SVSTATE at reset
0x0, # DEC at reset
# spot MTSPR, spot that DEC/TB is what is to be updated.
# a job for PowerDecoder2, there
if funame.lower().startswith('spr'):
- with m.If(fu.busy_o):
+ with m.If(fu.busy_o #& fu.oper_i.insn_type == OP_MTSPR
+ ):
comb += self.pause_dec_tb.eq(1)
# return both the function unit "enable" dict as well as the "busy".