conflict of access, regfile read/write hazards are *not* analysed,
and consequently it is safer to wait for the Function Unit to complete
before allowing a new instruction to proceed.
+(update: actually this is being added now:
+https://bugs.libre-soc.org/show_bug.cgi?id=737)
"""
from nmigen import (Elaboratable, Module, Signal, ResetSignal, Cat, Mux,
(pspec.allow_overlap == True))
# test core type
- self.make_hazard_vecs = True
+ self.make_hazard_vecs = self.allow_overlap
self.core_type = "fsm"
if hasattr(pspec, "core_type"):
self.core_type = pspec.core_type
regreduce_en=self.regreduce_en)
self.des[funame] = self.decoders[funame].do
+ # create per-Function Unit write-after-write hazard signals
+ # yes, really, this should have been added in ReservationStations
+ # but hey.
+ for funame, fu in self.fus.fus.items():
+ fu._waw_hazard = Signal(name="waw_%s" % funame)
+
# share the SPR decoder with the MMU if it exists
if "mmu0" in self.decoders:
self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
regs = self.regs
fus = self.fus.fus
+ # amalgamate write-hazards into a single top-level Signal
+ self.waw_hazard = Signal()
+ whaz = []
+ for funame, fu in self.fus.fus.items():
+ whaz.append(fu._waw_hazard)
+ comb += self.waw_hazard.eq(Cat(*whaz).bool())
+
# connect decoders
self.connect_satellite_decoders(m)
# connect each satellite decoder and give it the instruction.
# as subset decoders this massively reduces wire fanout given
# the large number of ALUs
- setattr(m.submodules, "dec_%s" % v.fn_name, v)
+ m.submodules["dec_%s" % v.fn_name] = v
comb += v.dec.raw_opcode_in.eq(self.ireg.raw_insn_i)
comb += v.dec.bigendian.eq(self.ireg.bigendian_i)
# sigh due to SVP64 RA_OR_ZERO detection connect these too
# issue, busy, read flags and mask to FU
with m.If(enable):
# operand comes from the *local* decoder
+ # do not actually issue, though, if there
+ # is a waw hazard. decoder has to still
+ # be asserted in order to detect that, tho
comb += fu.oper_i.eq_from(do)
- comb += fu.issue_i.eq(1) # issue when valid
+ # issue when valid (and no write-hazard)
+ comb += fu.issue_i.eq(~self.waw_hazard)
# instruction ok, indicate ready
comb += self.p.o_ready.eq(1)
if self.allow_overlap:
- with m.If(~fu_found):
+ with m.If(~fu_found | self.waw_hazard):
# latch copy of instruction
sync += ilatch.eq(self.i)
comb += self.p.o_ready.eq(1) # accept
# run this FunctionUnit if enabled route op,
# issue, busy, read flags and mask to FU
with m.If(enable):
- # operand comes from the *local* decoder
+ # operand comes from the *local* decoder,
+ # which is asserted even if not issued,
+ # so that WaW-detection can check for hazards.
+ # only if the waw hazard is clear does the
+ # instruction actually get issued
comb += fu.oper_i.eq_from(do)
- comb += fu.issue_i.eq(1) # issue when valid
- comb += self.p.o_ready.eq(1)
- comb += busy_o.eq(0)
- m.next = "READY"
+ # issue when valid
+ comb += fu.issue_i.eq(~self.waw_hazard)
+ with m.If(~self.waw_hazard):
+ comb += self.p.o_ready.eq(1)
+ comb += busy_o.eq(0)
+ m.next = "READY"
print ("core: overlap allowed", self.allow_overlap)
- busys = map(lambda fu: fu.busy_o, fus.values())
- comb += any_busy_o.eq(Cat(*busys).bool())
+ # true when any FU is busy (including the cycle where it is perhaps
+ # to be issued - because that's what fu_busy is)
+ comb += any_busy_o.eq(fu_busy.bool())
if not self.allow_overlap:
# for simple non-overlap, if any instruction is busy, set
# busy output for core.
# and resolved
with m.If(self.issue_conflict):
comb += busy_o.eq(1)
+ # make sure that LDST, SPR, MMU, Branch and Trap all say "busy"
+ # and do not allow overlap. these are all the ones that
+ # are non-forward-progressing: exceptions etc. that otherwise
+ # change CoreState for some reason (MSR, PC, SVSTATE)
+ for funame, fu in fus.items():
+ if (funame.lower().startswith('ldst') or
+ funame.lower().startswith('branch') or
+ funame.lower().startswith('mmu') or
+ funame.lower().startswith('spr') or
+ funame.lower().startswith('trap')):
+ with m.If(fu.busy_o):
+ comb += busy_o.eq(1)
# return both the function unit "enable" dict as well as the "busy".
# the "busy-or-issued" can be passed in to the Read/Write port
# for checking if the read port has an outstanding write
if self.make_hazard_vecs:
wv = regs.wv[regfile.lower()]
- wvchk = wv.r_ports["issue"] # write-vec bit-level hazard check
+ wvchk = wv.q_int # write-vec bit-level hazard check
# if a hazard is detected on this read port, simply blithely block
# every FU from reading on it. this is complete overkill but very
# create a priority picker to manage this port
rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
- setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
+ m.submodules["rdpick_%s_%s" % (regfile, rpidx)] = rdpick
rens = []
addrs = []
continue
# read the write-hazard bitvector (wv) for any bit that is
- wvchk_en = Signal(len(wvchk.ren), name="wv_chk_addr_en_"+name)
+ wvchk_en = Signal(len(wvchk), name="wv_chk_addr_en_"+name)
issue_active = Signal(name="rd_iactive_"+name)
# XXX combinatorial loop here
comb += issue_active.eq(fu_active & rf)
# read-hazard is ANDed with (filtered by) what is actually
# being requested.
- comb += rhazard.eq((wvchk.o_data & wvchk_en).bool())
+ comb += rhazard.eq((wvchk & wvchk_en).bool())
wvens.append(wvchk_en)
# enable the read bitvectors for this issued instruction
# and return whether any write-hazard bit is set
- comb += wvchk.ren.eq(ortreereduce_sig(wvens))
- comb += hazard_detected.eq(wvchk.o_data.bool())
+ wvchk_and = Signal(len(wvchk), name="wv_chk_"+name)
+ comb += wvchk_and.eq(wvchk & ortreereduce_sig(wvens))
+ comb += hazard_detected.eq(wvchk_and.bool())
return hazard_detected
def connect_rdports(self, m, fu_bitdict, fu_selected):
# the hazard)
# the detection of what shall be written to is based
- # on *issue*
+ # on *issue*. it is delayed by 1 cycle so that instructions
+ # "addi 5,5,0x2" do not cause combinatorial loops due to
+ # fake-dependency on *themselves*. this will totally fail
+ # spectacularly when doing multi-issue
print ("write vector (for regread)", regfile, wvset)
- wviaddr_en = Signal(len(wvset.wen), name="wv_issue_addr_en_"+name)
+ wviaddr_en = Signal(len(wvset), name="wv_issue_addr_en_"+name)
issue_active = Signal(name="iactive_"+name)
- comb += issue_active.eq(fu.issue_i & fu_active & wrflag)
+ sync += issue_active.eq(fu.issue_i & fu_active & wrflag)
with m.If(issue_active):
if rfile.unary:
comb += wviaddr_en.eq(write)
# deal with write vector clear: this kicks in when the regfile
# is written to, and clears the corresponding bitvector entry
print ("write vector", regfile, wvclr)
- wvaddr_en = Signal(len(wvclr.wen), name="wvaddr_en_"+name)
+ wvaddr_en = Signal(len(wvclr), name="wvaddr_en_"+name)
if rfile.unary:
comb += wvaddr_en.eq(addr_en)
else:
# to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
if self.make_hazard_vecs:
wv = regs.wv[regfile.lower()]
- wvset = wv.w_ports["set"] # write-vec bit-level hazard ctrl
- wvclr = wv.w_ports["clr"] # write-vec bit-level hazard ctrl
+ wvset = wv.s # write-vec bit-level hazard ctrl
+ wvclr = wv.r # write-vec bit-level hazard ctrl
+ wvchk = wv.q # write-after-write hazard check
+ wvchk_qint = wv.q # write-after-write hazard check, NOT delayed
fspecs = fspec
if not isinstance(fspecs, list):
# create a priority picker to manage this port
wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
- setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
+ m.submodules["wrpick_%s_%s" % (regfile, rpidx)] = wrpick
wsigs = []
wens = []
wvsets = []
wvseten = []
wvclren = []
+ #wvens = [] - not needed: reading of writevec is permanently held hi
addrs = []
for i, fspec in enumerate(fspecs):
# connect up the FU req/go signals and the reg-read to the FU
fspec.wid, fspec.specs)
for pi, fuspec in enumerate(fspec.specs):
(funame, fu, idx) = (fuspec.funame, fuspec.fu, fuspec.idx)
+ fu_requested = fu_bitdict[funame]
pi += ppoffs[i]
name = "%s_%s_%s_%d" % (funame, regfile, regname, idx)
# get (or set up) a write-latched copy of write register number
write = Signal.like(_write, name="write_"+name)
- rname = "%s_%s_%s" % (funame, regfile, regname)
+ rname = "%s_%s_%s_%d" % (funame, regfile, regname, idx)
if rname not in fu.wr_latches:
wrl = Signal.like(_write, name="wrlatch_"+rname)
fu.wr_latches[rname] = write
- with m.If(fu.issue_i):
+ # do not depend on fu.issue_i here, it creates a
+ # combinatorial loop on waw checking. using the FU
+ # "enable" bitdict entry for this FU is sufficient,
+ # because the PowerDecoder2 read/write nums are
+ # valid continuously when the instruction is valid
+ with m.If(fu_requested):
sync += wrl.eq(_write)
comb += write.eq(_write)
with m.Else():
# write-request comes from dest.ok
dest = fu.get_out(idx)
fu_dest_latch = fu.get_fu_out(idx) # latched output
- name = "fu_wrok_%s_%s_%d" % (funame, regname, idx)
- fu_wrok = Signal(name=name, reset_less=True)
+ name = "%s_%s_%d" % (funame, regname, idx)
+ fu_wrok = Signal(name="fu_wrok_"+name, reset_less=True)
comb += fu_wrok.eq(dest.ok & fu.busy_o)
# connect request-write to picker input, and output to go-wr
wvaddr_en, wv_issue_en = res
wvclren.append(wvaddr_en) # set only: no data => clear bit
wvseten.append(wv_issue_en) # set data same as enable
- wvsets.append(wv_issue_en) # because enable needs a 1
+
+ # read the write-hazard bitvector (wv) for any bit that is
+ fu_requested = fu_bitdict[funame]
+ wvchk_en = Signal(len(wvchk), name="waw_chk_addr_en_"+name)
+ issue_active = Signal(name="waw_iactive_"+name)
+ whazard = Signal(name="whaz_"+name)
+ if wf is None:
+ # XXX EEK! STATE regfile (branch) does not have an
+ # write-active indicator in regspec_decode_write()
+ print ("XXX FIXME waw_iactive", issue_active,
+ fu_requested, wf)
+ else:
+ # check bits from the incoming instruction. note (back
+ # in connect_instruction) that the decoder is held for
+ # us to be able to do this, here... *without* issue being
+ # held HI. we MUST NOT gate this with fu.issue_i or
+ # with fu_bitdict "enable": it would create a loop
+ comb += issue_active.eq(wf)
+ with m.If(issue_active):
+ if rfile.unary:
+ comb += wvchk_en.eq(write)
+ else:
+ comb += wvchk_en.eq(1<<write)
+ # if FU is busy (which doesn't get set at the same time as
+ # issue) and no hazard was detected, clear wvchk_en (i.e.
+ # stop checking for hazards). there is a loop here, but it's
+ # via a DFF, so is ok. some linters may complain, but hey.
+ with m.If(fu.busy_o & ~whazard):
+ comb += wvchk_en.eq(0)
+
+ # write-hazard is ANDed with (filtered by) what is actually
+ # being requested. the wvchk data is on a one-clock delay,
+ # and wvchk_en comes directly from the main decoder
+ comb += whazard.eq((wvchk_qint & wvchk_en).bool())
+ with m.If(whazard):
+ comb += fu._waw_hazard.eq(1)
+
+ #wvens.append(wvchk_en)
# here is where we create the Write Broadcast Bus. simple, eh?
comb += wport.i_data.eq(ortreereduce_sig(wsigs))
comb += wport.wen.eq(ortreereduce_sig(wens))
if not self.make_hazard_vecs:
- return
-
- # for write-vectors
- comb += wvclr.wen.eq(ortreereduce_sig(wvclren)) # clear (regfile write)
- comb += wvset.wen.eq(ortreereduce_sig(wvseten)) # set (issue time)
- comb += wvset.i_data.eq(ortreereduce_sig(wvsets))
+ return [], []
+
+ # return these here rather than set wvclr/wvset directly,
+ # because there may be more than one write-port to a given
+ # regfile. example: XER has a write-port for SO, CA, and OV
+ # and the *last one added* of those would overwrite the other
+ # two. solution: have connect_wrports collate all the
+ # or-tree-reduced bitvector set/clear requests and drop them
+ # in as a single "thing". this can only be done because the
+ # set/get is an unary bitvector.
+ print ("make write-vecs", regfile, regname, wvset, wvclr)
+ return (ortreereduce_sig(wvclren), # clear (regfile write)
+ ortreereduce_sig(wvseten)) # set (issue time)
def connect_wrports(self, m, fu_bitdict, fu_selected):
"""connect write ports
# same for write ports.
# BLECH! complex code-duplication! BLECH!
wrpickers = {}
+ wvclrers = defaultdict(list)
+ wvseters = defaultdict(list)
for regfile, spec in byregfiles_wr.items():
fuspecs = byregfiles_wrspec[regfile]
wrpickers[regfile] = {}
if 'fast3' in fuspecs:
fuspecs['fast1'].append(fuspecs.pop('fast3'))
+ # collate these and record them by regfile because there
+ # are sometimes more write-ports per regfile
for (regname, fspec) in sort_fuspecs(fuspecs):
- self.connect_wrport(m, fu_bitdict, fu_selected, wrpickers,
+ wvclren, wvseten = self.connect_wrport(m,
+ fu_bitdict, fu_selected,
+ wrpickers,
regfile, regname, fspec)
+ wvclrers[regfile.lower()].append(wvclren)
+ wvseters[regfile.lower()].append(wvseten)
+
+ if not self.make_hazard_vecs:
+ return
+
+ # for write-vectors: reduce the clr-ers and set-ers down to
+ # a single set of bits. otherwise if there are two write
+ # ports (on some regfiles), the last one doing comb += on
+ # the reg.wv[regfile] instance "wins" (and all others are ignored,
+ # whoops). if there was only one write-port per wv regfile this would
+ # not be an issue.
+ for regfile in wvclrers.keys():
+ wv = regs.wv[regfile]
+ wvset = wv.s # write-vec bit-level hazard ctrl
+ wvclr = wv.r # write-vec bit-level hazard ctrl
+ wvclren = wvclrers[regfile]
+ wvseten = wvseters[regfile]
+ comb += wvclr.eq(ortreereduce_sig(wvclren)) # clear (regfile write)
+ comb += wvset.eq(ortreereduce_sig(wvseten)) # set (issue time)
def get_byregfiles(self, readmode):
pspec = TestMemPspec(ldst_ifacetype='testpi',
imem_ifacetype='',
addr_wid=48,
+ allow_overlap=True,
mask_wid=8,
reg_wid=64)
dut = NonProductionCore(pspec)
projects / soc.git / blobdiff