fix write-after-write hazard checking

[soc.git] / src / soc / simple / core.py

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index f73017c443df0ff03ca534921c512d1f647437f6..debff9da1d6b37ea55dcb018bc9476b5fe25a25f 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -752,7 +752,7 @@ class NonProductionCore(ControlBase):
             wvset = wv.s # write-vec bit-level hazard ctrl
             wvclr = wv.r # write-vec bit-level hazard ctrl
             wvchk = wv.q # write-after-write hazard check
-            wvchk_qint = wv.q_int # write-after-write hazard check, delayed
+            wvchk_qint = wv.q # write-after-write hazard check, NOT delayed
 
         fspecs = fspec
         if not isinstance(fspecs, list):
@@ -985,6 +985,9 @@ class NonProductionCore(ControlBase):
                 wvclrers[regfile.lower()].append(wvclren)
                 wvseters[regfile.lower()].append(wvseten)
 
+        if not self.make_hazard_vecs:
+            return
+
         # for write-vectors: reduce the clr-ers and set-ers down to
         # a single set of bits.  otherwise if there are two write
         # ports (on some regfiles), the last one doing comb += on
@@ -1091,6 +1094,7 @@ if __name__ == '__main__':
     pspec = TestMemPspec(ldst_ifacetype='testpi',
                          imem_ifacetype='',
                          addr_wid=48,
+                         allow_overlap=True,
                          mask_wid=8,
                          reg_wid=64)
     dut = NonProductionCore(pspec)