def __init__(self, pspec):
+ # test if microwatt compatibility is to be enabled
+ self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
+ (pspec.microwatt_compat == True))
+ self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+
# test is SVP64 is to be enabled
self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
self.xics_icp = XICS_ICP()
self.xics_ics = XICS_ICS()
self.int_level_i = self.xics_ics.int_level_i
+ else:
+ self.ext_irq = Signal()
# add GPIO peripheral?
self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
self.srcmask = Signal(64)
self.dstmask = Signal(64)
+ # sigh, the wishbone addresses are not wishbone-compliant in microwatt
+ if self.microwatt_compat:
+ self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
+ self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
+
def setup_peripherals(self, m):
comb, sync = m.d.comb, m.d.sync
csd = DomainRenamer(self.core_domain)
dbd = DomainRenamer(self.dbg_domain)
- m.submodules.core = core = csd(self.core)
+ if self.microwatt_compat:
+ m.submodules.core = core = self.core
+ else:
+ m.submodules.core = core = csd(self.core)
# this _so_ needs sorting out. ICache is added down inside
# LoadStore1 and is already a submodule of LoadStore1
if not isinstance(self.imem, ICache):
# see https://bugs.libre-soc.org/show_bug.cgi?id=499
sync += dbg.dmi.connect_to(jtag.dmi)
+ # fixup the clocks in microwatt-compat mode (but leave resets alone
+ # so that microwatt soc.vhdl can pull a reset on the core or DMI
+ # can do it, just like in TestIssuer)
+ if self.microwatt_compat:
+ intclk = ClockSignal(self.core_domain)
+ dbgclk = ClockSignal(self.dbg_domain)
+ if self.core_domain != 'sync':
+ comb += intclk.eq(ClockSignal())
+ if self.dbg_domain != 'sync':
+ comb += dbgclk.eq(ClockSignal())
+
+ # drop the first 3 bits of the incoming wishbone addresses
+ # this can go if using later versions of microwatt (not now)
+ if self.microwatt_compat:
+ ibus = self.imem.ibus
+ dbus = self.core.l0.cmpi.wb_bus()
+ comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+ comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+
cur_state = self.cur_state
# 4x 4k SRAM blocks. these simply "exist", they get routed in litex
m.submodules.xics_ics = ics = csd(self.xics_ics)
comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
+ else:
+ sync += cur_state.eint.eq(self.ext_irq) # connect externally
# GPIO test peripheral
if self.gpio:
comb += self.state_w_sv.i_data.eq(self.new_svstate)
sync += self.sv_changed.eq(1)
+ # start renaming some of the ports to match microwatt
+ if self.microwatt_compat:
+ self.core.o.core_terminate_o.name = "terminated_out"
+ # names of DMI interface
+ self.dbg.dmi.addr_i.name = 'dmi_addr'
+ self.dbg.dmi.din.name = 'dmi_din'
+ self.dbg.dmi.dout.name = 'dmi_dout'
+ self.dbg.dmi.req_i.name = 'dmi_req'
+ self.dbg.dmi.we_i.name = 'dmi_wr'
+ self.dbg.dmi.ack_o.name = 'dmi_ack'
+ # wishbone instruction bus
+ ibus = self.imem.ibus
+ ibus.adr.name = 'wishbone_insn_out.adr'
+ ibus.dat_w.name = 'wishbone_insn_out.dat'
+ ibus.sel.name = 'wishbone_insn_out.sel'
+ ibus.cyc.name = 'wishbone_insn_out.cyc'
+ ibus.stb.name = 'wishbone_insn_out.stb'
+ ibus.we.name = 'wishbone_insn_out.we'
+ ibus.dat_r.name = 'wishbone_insn_in.dat'
+ ibus.ack.name = 'wishbone_insn_in.ack'
+ ibus.stall.name = 'wishbone_insn_in.stall'
+ # wishbone data bus
+ dbus = self.core.l0.cmpi.wb_bus()
+ dbus.adr.name = 'wishbone_data_out.adr'
+ dbus.dat_w.name = 'wishbone_data_out.dat'
+ dbus.sel.name = 'wishbone_data_out.sel'
+ dbus.cyc.name = 'wishbone_data_out.cyc'
+ dbus.stb.name = 'wishbone_data_out.stb'
+ dbus.we.name = 'wishbone_data_out.we'
+ dbus.dat_r.name = 'wishbone_data_in.dat'
+ dbus.ack.name = 'wishbone_data_in.ack'
+ dbus.stall.name = 'wishbone_data_in.stall'
+
return m
def __iter__(self):
return list(self)
def external_ports(self):
+ if self.microwatt_compat:
+ ports = [self.core.o.core_terminate_o,
+ self.ext_irq,
+ self.alt_reset, # not connected yet
+ ClockSignal(),
+ ResetSignal(),
+ ]
+ ports += list(self.dbg.dmi.ports())
+ # for dbus/ibus microwatt, exclude err btw and cti
+ for name, sig in self.imem.ibus.fields.items():
+ if name not in ['err', 'bte', 'cti', 'adr']:
+ ports.append(sig)
+ for name, sig in self.core.l0.cmpi.wb_bus().fields.items():
+ if name not in ['err', 'bte', 'cti', 'adr']:
+ ports.append(sig)
+ # microwatt non-compliant with wishbone
+ ports.append(self.ibus_adr)
+ ports.append(self.dbus_adr)
+ return ports
+
ports = self.pc_i.ports()
ports = self.msr_i.ports()
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
ports += list(self.xics_icp.bus.fields.values())
ports += list(self.xics_ics.bus.fields.values())
ports.append(self.int_level_i)
+ else:
+ ports.append(self.ext_irq)
if self.gpio:
ports += list(self.simple_gpio.bus.fields.values())
# set priv / virt mode on I-Cache, sigh
if isinstance(self.imem, ICache):
comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
- comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR])
+ comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
with m.FSM(name='fetch_fsm'):
# waiting (zzz)
with m.State("IDLE"):
- with m.If(~dbg.stopping_o & ~fetch_failed & ~dbg.core_stop_o):
+ # fetch allowed if not failed and stopped but not stepping
+ # (see dmi.py for how core_stop_o is generated)
+ with m.If(~fetch_failed & ~dbg.core_stop_o):
comb += fetch_pc_o_ready.eq(1)
with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault
& ~dbg.core_stop_o):
# dummy pause to find out why simulation is not keeping up
with m.State("INSN_READ"):
- if self.allow_overlap:
- stopping = dbg.stopping_o
- else:
- stopping = Const(0)
+ # when using "single-step" mode, checking dbg.stopping_o
+ # prevents progress. allow fetch to proceed once started
+ stopping = Const(0)
+ #if self.allow_overlap:
+ # stopping = dbg.stopping_o
with m.If(stopping):
# stopping: jump back to idle
m.next = "IDLE"
with m.If(self.imem.f_busy_o &
~pdecode2.instr_fault): # zzz...
# busy but not fetch failed: stay in wait-read
+ comb += self.imem.a_pc_i.eq(pc)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
with m.Else():
comb += self.imem.f_i_valid.eq(1)
with m.Else():
# not busy: instruction fetched
- insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
+ if hasattr(core, "icache"):
+ # blech, icache returns actual instruction
+ insn = self.imem.f_instr_o
+ else:
+ insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
sync += dec_opcode_o.eq(insn)
m.next = "INSN_READY"
# TODO: probably can start looking at pdecode2.rm_dec
# wait for an instruction to arrive from Fetch
with m.State("INSN_WAIT"):
- if self.allow_overlap:
- stopping = dbg.stopping_o
- else:
- stopping = Const(0)
+ # when using "single-step" mode, checking dbg.stopping_o
+ # prevents progress. allow issue to proceed once started
+ stopping = Const(0)
+ #if self.allow_overlap:
+ # stopping = dbg.stopping_o
with m.If(stopping):
# stopping: jump back to idle
m.next = "ISSUE_START"
# handshake with execution FSM, move to "wait" once acknowledged
with m.State("INSN_EXECUTE"):
- if self.allow_overlap:
- stopping = dbg.stopping_o
- else:
- stopping = Const(0)
+ # when using "single-step" mode, checking dbg.stopping_o
+ # prevents progress. allow execute to proceed once started
+ stopping = Const(0)
+ #if self.allow_overlap:
+ # stopping = dbg.stopping_o
with m.If(stopping):
# stopping: jump back to idle
m.next = "ISSUE_START"
m.next = "EXECUTE_WAIT"
with m.State("EXECUTE_WAIT"):
- # wait on "core stop" release, at instruction end
- # need to do this here, in case we are in a VL>1 loop
- with m.If(~dbg.core_stop_o & ~core_rst):
- comb += exec_pc_i_ready.eq(1)
- # see https://bugs.libre-soc.org/show_bug.cgi?id=636
- # the exception info needs to be blatted into
- # pdecode.ldst_exc, and the instruction "re-run".
- # when ldst_exc.happened is set, the PowerDecoder2
- # reacts very differently: it re-writes the instruction
- # with a "trap" (calls PowerDecoder2.trap()) which
- # will *overwrite* whatever was requested and jump the
- # PC to the exception address, as well as alter MSR.
- # nothing else needs to be done other than to note
- # the change of PC and MSR (and, later, SVSTATE)
- with m.If(exc_happened):
- mmu = core.fus.get_exc("mmu0")
- ldst = core.fus.get_exc("ldst0")
- if mmu is not None:
- with m.If(fetch_failed):
- # instruction fetch: exception is from MMU
- # reset instr_fault (highest priority)
- sync += pdecode2.ldst_exc.eq(mmu)
- sync += pdecode2.instr_fault.eq(0)
- if flush_needed:
- # request icache to stop asserting "failed"
- comb += core.icache.flush_in.eq(1)
- with m.If(~fetch_failed):
- # otherwise assume it was a LDST exception
- sync += pdecode2.ldst_exc.eq(ldst)
-
- with m.If(exec_pc_o_valid):
-
- # was this the last loop iteration?
- is_last = Signal()
- cur_vl = cur_state.svstate.vl
- comb += is_last.eq(next_srcstep == cur_vl)
-
- with m.If(pdecode2.instr_fault):
- # reset instruction fault, try again
+ comb += exec_pc_i_ready.eq(1)
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=636
+ # the exception info needs to be blatted into
+ # pdecode.ldst_exc, and the instruction "re-run".
+ # when ldst_exc.happened is set, the PowerDecoder2
+ # reacts very differently: it re-writes the instruction
+ # with a "trap" (calls PowerDecoder2.trap()) which
+ # will *overwrite* whatever was requested and jump the
+ # PC to the exception address, as well as alter MSR.
+ # nothing else needs to be done other than to note
+ # the change of PC and MSR (and, later, SVSTATE)
+ with m.If(exc_happened):
+ mmu = core.fus.get_exc("mmu0")
+ ldst = core.fus.get_exc("ldst0")
+ if mmu is not None:
+ with m.If(fetch_failed):
+ # instruction fetch: exception is from MMU
+ # reset instr_fault (highest priority)
+ sync += pdecode2.ldst_exc.eq(mmu)
sync += pdecode2.instr_fault.eq(0)
- m.next = "ISSUE_START"
+ if flush_needed:
+ # request icache to stop asserting "failed"
+ comb += core.icache.flush_in.eq(1)
+ with m.If(~fetch_failed):
+ # otherwise assume it was a LDST exception
+ sync += pdecode2.ldst_exc.eq(ldst)
+
+ with m.If(exec_pc_o_valid):
+
+ # was this the last loop iteration?
+ is_last = Signal()
+ cur_vl = cur_state.svstate.vl
+ comb += is_last.eq(next_srcstep == cur_vl)
+
+ with m.If(pdecode2.instr_fault):
+ # reset instruction fault, try again
+ sync += pdecode2.instr_fault.eq(0)
+ m.next = "ISSUE_START"
- # return directly to Decode if Execute generated an
- # exception.
- with m.Elif(pdecode2.ldst_exc.happened):
- m.next = "DECODE_SV"
+ # return directly to Decode if Execute generated an
+ # exception.
+ with m.Elif(pdecode2.ldst_exc.happened):
+ m.next = "DECODE_SV"
- # if MSR, PC or SVSTATE were changed by the previous
- # instruction, go directly back to Fetch, without
- # updating either MSR PC or SVSTATE
- with m.Elif(self.msr_changed | self.pc_changed |
- self.sv_changed):
- m.next = "ISSUE_START"
+ # if MSR, PC or SVSTATE were changed by the previous
+ # instruction, go directly back to Fetch, without
+ # updating either MSR PC or SVSTATE
+ with m.Elif(self.msr_changed | self.pc_changed |
+ self.sv_changed):
+ m.next = "ISSUE_START"
- # also return to Fetch, when no output was a vector
- # (regardless of SRCSTEP and VL), or when the last
- # instruction was really the last one of the VL loop
- with m.Elif((~pdecode2.loop_continue) | is_last):
- # before going back to fetch, update the PC state
- # register with the NIA.
- # ok here we are not reading the branch unit.
- # TODO: this just blithely overwrites whatever
- # pipeline updated the PC
- comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.i_data.eq(nia)
- # reset SRCSTEP before returning to Fetch
- if self.svp64_en:
- with m.If(pdecode2.loop_continue):
- comb += new_svstate.srcstep.eq(0)
- comb += new_svstate.dststep.eq(0)
- comb += self.update_svstate.eq(1)
- else:
+ # also return to Fetch, when no output was a vector
+ # (regardless of SRCSTEP and VL), or when the last
+ # instruction was really the last one of the VL loop
+ with m.Elif((~pdecode2.loop_continue) | is_last):
+ # before going back to fetch, update the PC state
+ # register with the NIA.
+ # ok here we are not reading the branch unit.
+ # TODO: this just blithely overwrites whatever
+ # pipeline updated the PC
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.i_data.eq(nia)
+ # reset SRCSTEP before returning to Fetch
+ if self.svp64_en:
+ with m.If(pdecode2.loop_continue):
comb += new_svstate.srcstep.eq(0)
comb += new_svstate.dststep.eq(0)
comb += self.update_svstate.eq(1)
- m.next = "ISSUE_START"
-
- # returning to Execute? then, first update SRCSTEP
- with m.Else():
- comb += new_svstate.srcstep.eq(next_srcstep)
- comb += new_svstate.dststep.eq(next_dststep)
+ else:
+ comb += new_svstate.srcstep.eq(0)
+ comb += new_svstate.dststep.eq(0)
comb += self.update_svstate.eq(1)
- # return to mask skip loop
- m.next = "PRED_SKIP"
-
- with m.Else():
- comb += dbg.core_stopped_i.eq(1)
- if flush_needed:
- # request the icache to stop asserting "failed"
- comb += core.icache.flush_in.eq(1)
- # stop instruction fault
- sync += pdecode2.instr_fault.eq(0)
- # if terminated return to idle
- with m.If(dbg.terminate_i):
m.next = "ISSUE_START"
+ # returning to Execute? then, first update SRCSTEP
+ with m.Else():
+ comb += new_svstate.srcstep.eq(next_srcstep)
+ comb += new_svstate.dststep.eq(next_dststep)
+ comb += self.update_svstate.eq(1)
+ # return to mask skip loop
+ m.next = "PRED_SKIP"
+
+
# check if svstate needs updating: if so, write it to State Regfile
with m.If(self.update_svstate):
sync += cur_state.svstate.eq(self.new_svstate) # for next clock
class TestIssuer(Elaboratable):
def __init__(self, pspec):
self.ti = TestIssuerInternal(pspec)
- # XXX TODO: make this a command-line selectable option from pspec
- #from soc.simple.inorder import TestIssuerInternalInOrder
- #self.ti = TestIssuerInternalInOrder(pspec)
self.pll = DummyPLL(instance=True)
self.dbg_rst_i = Signal(reset_less=True)
projects / soc.git / blobdiff