from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
SVP64PredMode)
from openpower.state import CoreState
-from openpower.consts import (CR, SVP64CROffs)
+from openpower.consts import (CR, SVP64CROffs, MSR)
from soc.experiment.testmem import TestMemory # test only for instructions
from soc.regfile.regfiles import StateRegs, FastRegs
from soc.simple.core import NonProductionCore
def __init__(self, pspec):
+ # test if microwatt compatibility is to be enabled
+ self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
+ (pspec.microwatt_compat == True))
+ self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+
# test is SVP64 is to be enabled
self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
self.allow_overlap = (hasattr(pspec, "allow_overlap") and
(pspec.allow_overlap == True))
+ # and get the core domain
+ self.core_domain = "coresync"
+ if (hasattr(pspec, "core_domain") and
+ isinstance(pspec.core_domain, str)):
+ self.core_domain = pspec.core_domain
+
# JTAG interface. add this right at the start because if it's
# added it *modifies* the pspec, by adding enable/disable signals
# for parts of the rest of the core
self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
- self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
- # self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
+ #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
+ self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
if self.jtag_en:
# XXX MUST keep this up-to-date with litex, and
# soc-cocotb-sim, and err.. all needs sorting out, argh
self.xics_icp = XICS_ICP()
self.xics_ics = XICS_ICS()
self.int_level_i = self.xics_ics.int_level_i
+ else:
+ self.ext_irq = Signal()
# add GPIO peripheral?
self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
# main instruction core. suitable for prototyping / demo only
self.core = core = NonProductionCore(pspec)
- self.core_rst = ResetSignal("coresync")
+ self.core_rst = ResetSignal(self.core_domain)
# instruction decoder. goes into Trap Record
#pdecode = create_pdecode()
if self.svp64_en:
self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
+ self.update_svstate = Signal() # set this if updating svstate
+ self.new_svstate = new_svstate = SVSTATERec("new_svstate")
+
# Test Instruction memory
if hasattr(core, "icache"):
# XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
# DMI interface
self.dbg = CoreDebug()
+ self.dbg_rst_i = Signal(reset_less=True)
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.srcmask = Signal(64)
self.dstmask = Signal(64)
+ # sigh, the wishbone addresses are not wishbone-compliant in microwatt
+ if self.microwatt_compat:
+ self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
+ self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
+
def setup_peripherals(self, m):
comb, sync = m.d.comb, m.d.sync
# but NOT its reset signal. to cope with this, set every single
# submodule explicitly in coresync domain, debug and JTAG
# in their own one but using *external* reset.
- csd = DomainRenamer("coresync")
+ csd = DomainRenamer(self.core_domain)
dbd = DomainRenamer(self.dbg_domain)
- m.submodules.core = core = csd(self.core)
+ if self.microwatt_compat:
+ m.submodules.core = core = self.core
+ else:
+ m.submodules.core = core = csd(self.core)
# this _so_ needs sorting out. ICache is added down inside
# LoadStore1 and is already a submodule of LoadStore1
if not isinstance(self.imem, ICache):
# see https://bugs.libre-soc.org/show_bug.cgi?id=499
sync += dbg.dmi.connect_to(jtag.dmi)
+ # fixup the clocks in microwatt-compat mode (but leave resets alone
+ # so that microwatt soc.vhdl can pull a reset on the core or DMI
+ # can do it, just like in TestIssuer)
+ if self.microwatt_compat:
+ intclk = ClockSignal(self.core_domain)
+ dbgclk = ClockSignal(self.dbg_domain)
+ if self.core_domain != 'sync':
+ comb += intclk.eq(ClockSignal())
+ if self.dbg_domain != 'sync':
+ comb += dbgclk.eq(ClockSignal())
+
+ # drop the first 3 bits of the incoming wishbone addresses
+ # this can go if using later versions of microwatt (not now)
+ if self.microwatt_compat:
+ ibus = self.imem.ibus
+ dbus = self.core.l0.cmpi.wb_bus()
+ comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+ comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+
cur_state = self.cur_state
# 4x 4k SRAM blocks. these simply "exist", they get routed in litex
m.submodules.xics_ics = ics = csd(self.xics_ics)
comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
+ else:
+ sync += cur_state.eint.eq(self.ext_irq) # connect externally
# GPIO test peripheral
if self.gpio:
# clock delay power-on reset
cd_por = ClockDomain(reset_less=True)
cd_sync = ClockDomain()
- core_sync = ClockDomain("coresync")
- m.domains += cd_por, cd_sync, core_sync
+ m.domains += cd_por, cd_sync
+ core_sync = ClockDomain(self.core_domain)
+ if self.core_domain != "sync":
+ m.domains += core_sync
if self.dbg_domain != "sync":
dbg_sync = ClockDomain(self.dbg_domain)
m.domains += dbg_sync
comb += cd_por.clk.eq(ClockSignal())
# power-on reset delay
- core_rst = ResetSignal("coresync")
- comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
- comb += core_rst.eq(ti_rst)
+ core_rst = ResetSignal(self.core_domain)
+ if self.core_domain != "sync":
+ comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
+ comb += core_rst.eq(ti_rst)
+ else:
+ with m.If(delay != 0 | dbg.core_rst_o):
+ comb += core_rst.eq(1)
- # debug clock is same as coresync, but reset is *main external*
+ # connect external reset signal to DMI Reset
if self.dbg_domain != "sync":
dbg_rst = ResetSignal(self.dbg_domain)
- comb += dbg_rst.eq(ResetSignal())
+ comb += dbg_rst.eq(self.dbg_rst_i)
# busy/halted signals from core
core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o # core is busy
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
+ # check halted condition: requested PC to execute matches DMI stop addr
+ # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
+ # match
+ halted = Signal()
+ comb += halted.eq(dbg.stop_addr_o == dbg.state.pc)
+ with m.If(halted):
+ comb += dbg.core_stopped_i.eq(1)
+ comb += dbg.terminate_i.eq(1)
+
# PC and instruction from I-Memory
comb += self.pc_o.eq(cur_state.pc)
self.pc_changed = Signal() # note write to PC
# (which uses that in PowerDecoder2 to raise 0x900 exception)
self.tb_dec_fsm(m, cur_state.dec)
+ # while stopped, allow updating the MSR, PC and SVSTATE.
+ # these are mainly for debugging purposes (including DMI/JTAG)
+ with m.If(dbg.core_stopped_i):
+ with m.If(self.pc_i.ok):
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.i_data.eq(self.pc_i.data)
+ sync += self.pc_changed.eq(1)
+ with m.If(self.msr_i.ok):
+ comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
+ comb += self.state_w_msr.i_data.eq(self.msr_i.data)
+ sync += self.msr_changed.eq(1)
+ with m.If(self.svstate_i.ok | self.update_svstate):
+ with m.If(self.svstate_i.ok): # over-ride from external source
+ comb += self.new_svstate.eq(self.svstate_i.data)
+ comb += self.state_w_sv.wen.eq(1 << StateRegs.SVSTATE)
+ comb += self.state_w_sv.i_data.eq(self.new_svstate)
+ sync += self.sv_changed.eq(1)
+
+ # start renaming some of the ports to match microwatt
+ if self.microwatt_compat:
+ self.core.o.core_terminate_o.name = "terminated_out"
+ # names of DMI interface
+ self.dbg.dmi.addr_i.name = 'dmi_addr'
+ self.dbg.dmi.din.name = 'dmi_din'
+ self.dbg.dmi.dout.name = 'dmi_dout'
+ self.dbg.dmi.req_i.name = 'dmi_req'
+ self.dbg.dmi.we_i.name = 'dmi_wr'
+ self.dbg.dmi.ack_o.name = 'dmi_ack'
+ # wishbone instruction bus
+ ibus = self.imem.ibus
+ ibus.adr.name = 'wishbone_insn_out.adr'
+ ibus.dat_w.name = 'wishbone_insn_out.dat'
+ ibus.sel.name = 'wishbone_insn_out.sel'
+ ibus.cyc.name = 'wishbone_insn_out.cyc'
+ ibus.stb.name = 'wishbone_insn_out.stb'
+ ibus.we.name = 'wishbone_insn_out.we'
+ ibus.dat_r.name = 'wishbone_insn_in.dat'
+ ibus.ack.name = 'wishbone_insn_in.ack'
+ ibus.stall.name = 'wishbone_insn_in.stall'
+ # wishbone data bus
+ dbus = self.core.l0.cmpi.wb_bus()
+ dbus.adr.name = 'wishbone_data_out.adr'
+ dbus.dat_w.name = 'wishbone_data_out.dat'
+ dbus.sel.name = 'wishbone_data_out.sel'
+ dbus.cyc.name = 'wishbone_data_out.cyc'
+ dbus.stb.name = 'wishbone_data_out.stb'
+ dbus.we.name = 'wishbone_data_out.we'
+ dbus.dat_r.name = 'wishbone_data_in.dat'
+ dbus.ack.name = 'wishbone_data_in.ack'
+ dbus.stall.name = 'wishbone_data_in.stall'
+
return m
def __iter__(self):
return list(self)
def external_ports(self):
+ if self.microwatt_compat:
+ ports = [self.core.o.core_terminate_o,
+ self.ext_irq,
+ self.alt_reset, # not connected yet
+ ClockSignal(),
+ ResetSignal(),
+ ]
+ ports += list(self.dbg.dmi.ports())
+ # for dbus/ibus microwatt, exclude err btw and cti
+ for name, sig in self.imem.ibus.fields.items():
+ if name not in ['err', 'bte', 'cti', 'adr']:
+ ports.append(sig)
+ for name, sig in self.core.l0.cmpi.wb_bus().fields.items():
+ if name not in ['err', 'bte', 'cti', 'adr']:
+ ports.append(sig)
+ # microwatt non-compliant with wishbone
+ ports.append(self.ibus_adr)
+ ports.append(self.dbus_adr)
+ return ports
+
ports = self.pc_i.ports()
ports = self.msr_i.ports()
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
ports += list(self.xics_icp.bus.fields.values())
ports += list(self.xics_ics.bus.fields.values())
ports.append(self.int_level_i)
+ else:
+ ports.append(self.ext_irq)
if self.gpio:
ports += list(self.simple_gpio.bus.fields.values())
fetch_failed = Const(0, 1)
flush_needed = False
+ # set priv / virt mode on I-Cache, sigh
+ if isinstance(self.imem, ICache):
+ comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
+ comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
+
with m.FSM(name='fetch_fsm'):
# waiting (zzz)
with m.State("IDLE"):
- with m.If(~dbg.stopping_o & ~fetch_failed):
+ # fetch allowed if not failed and stopped but not stepping
+ # (see dmi.py for how core_stop_o is generated)
+ with m.If(~fetch_failed & ~dbg.core_stop_o):
comb += fetch_pc_o_ready.eq(1)
- with m.If(fetch_pc_i_valid & ~fetch_failed):
+ with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault
+ & ~dbg.core_stop_o):
# instruction allowed to go: start by reading the PC
# capture the PC and also drop it into Insn Memory
# we have joined a pair of combinatorial memory
comb += self.imem.a_pc_i.eq(pc)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
+ # transfer state to output
sync += cur_state.pc.eq(pc)
sync += cur_state.svstate.eq(svstate) # and svstate
sync += cur_state.msr.eq(msr) # and msr
# dummy pause to find out why simulation is not keeping up
with m.State("INSN_READ"):
- if self.allow_overlap:
- stopping = dbg.stopping_o
- else:
- stopping = Const(0)
+ # when using "single-step" mode, checking dbg.stopping_o
+ # prevents progress. allow fetch to proceed once started
+ stopping = Const(0)
+ #if self.allow_overlap:
+ # stopping = dbg.stopping_o
with m.If(stopping):
# stopping: jump back to idle
m.next = "IDLE"
with m.Else():
- with m.If(self.imem.f_busy_o & ~fetch_failed): # zzz...
+ with m.If(self.imem.f_busy_o &
+ ~pdecode2.instr_fault): # zzz...
# busy but not fetch failed: stay in wait-read
+ comb += self.imem.a_pc_i.eq(pc)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
with m.Else():
# not busy (or fetch failed!): instruction fetched
# when fetch failed, the instruction gets ignored
# by the decoder
- insn = get_insn(self.imem.f_instr_o, cur_state.pc)
+ if hasattr(core, "icache"):
+ # blech, icache returns actual instruction
+ insn = self.imem.f_instr_o
+ else:
+ # but these return raw memory
+ insn = get_insn(self.imem.f_instr_o, cur_state.pc)
if self.svp64_en:
svp64 = self.svp64
# decode the SVP64 prefix, if any
comb += self.imem.f_i_valid.eq(1)
with m.Else():
# not busy: instruction fetched
- insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
+ if hasattr(core, "icache"):
+ # blech, icache returns actual instruction
+ insn = self.imem.f_instr_o
+ else:
+ insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
sync += dec_opcode_o.eq(insn)
m.next = "INSN_READY"
# TODO: probably can start looking at pdecode2.rm_dec
sync = m.d.sync
pdecode2 = self.pdecode2
cur_state = self.cur_state
+ new_svstate = self.new_svstate
# temporaries
dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
# for updating svstate (things like srcstep etc.)
- update_svstate = Signal() # set this (below) if updating
- new_svstate = SVSTATERec("new_svstate")
comb += new_svstate.eq(cur_state.svstate)
# precalculate srcstep+1 and dststep+1
with m.Else():
# tell core it's stopped, and acknowledge debug handshake
comb += dbg.core_stopped_i.eq(1)
- # while stopped, allow updating the MSR, PC and SVSTATE
- with m.If(self.pc_i.ok):
- comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.i_data.eq(self.pc_i.data)
- sync += self.pc_changed.eq(1)
- with m.If(self.msr_i.ok):
- comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
- comb += self.state_w_msr.i_data.eq(self.msr_i.data)
- sync += self.msr_changed.eq(1)
+ # while stopped, allow updating SVSTATE
with m.If(self.svstate_i.ok):
comb += new_svstate.eq(self.svstate_i.data)
- comb += update_svstate.eq(1)
+ comb += self.update_svstate.eq(1)
sync += self.sv_changed.eq(1)
# wait for an instruction to arrive from Fetch
with m.State("INSN_WAIT"):
- if self.allow_overlap:
- stopping = dbg.stopping_o
- else:
- stopping = Const(0)
+ # when using "single-step" mode, checking dbg.stopping_o
+ # prevents progress. allow issue to proceed once started
+ stopping = Const(0)
+ #if self.allow_overlap:
+ # stopping = dbg.stopping_o
with m.If(stopping):
# stopping: jump back to idle
m.next = "ISSUE_START"
comb += self.state_w_pc.i_data.eq(nia)
comb += new_svstate.srcstep.eq(0)
comb += new_svstate.dststep.eq(0)
- comb += update_svstate.eq(1)
+ comb += self.update_svstate.eq(1)
# synchronize with the simulator
comb += self.insn_done.eq(1)
# go back to Issue
# update new src/dst step
comb += new_svstate.srcstep.eq(skip_srcstep)
comb += new_svstate.dststep.eq(skip_dststep)
- comb += update_svstate.eq(1)
+ comb += self.update_svstate.eq(1)
# proceed to Decode
m.next = "DECODE_SV"
# handshake with execution FSM, move to "wait" once acknowledged
with m.State("INSN_EXECUTE"):
- comb += exec_insn_i_valid.eq(1) # trigger execute
- with m.If(exec_insn_o_ready): # execute acknowledged us
- m.next = "EXECUTE_WAIT"
-
- with m.State("EXECUTE_WAIT"):
- # wait on "core stop" release, at instruction end
- # need to do this here, in case we are in a VL>1 loop
- with m.If(~dbg.core_stop_o & ~core_rst):
- comb += exec_pc_i_ready.eq(1)
- # see https://bugs.libre-soc.org/show_bug.cgi?id=636
- # the exception info needs to be blatted into
- # pdecode.ldst_exc, and the instruction "re-run".
- # when ldst_exc.happened is set, the PowerDecoder2
- # reacts very differently: it re-writes the instruction
- # with a "trap" (calls PowerDecoder2.trap()) which
- # will *overwrite* whatever was requested and jump the
- # PC to the exception address, as well as alter MSR.
- # nothing else needs to be done other than to note
- # the change of PC and MSR (and, later, SVSTATE)
- with m.If(exc_happened):
- mmu = core.fus.get_exc("mmu0")
- ldst = core.fus.get_exc("ldst0")
- if mmu is not None:
- with m.If(fetch_failed):
- # instruction fetch: exception is from MMU
- # reset instr_fault (highest priority)
- sync += pdecode2.ldst_exc.eq(mmu)
- sync += pdecode2.instr_fault.eq(0)
- if flush_needed:
- # request icache to stop asserting "failed"
- comb += core.icache.flush_in.eq(1)
- with m.If(~fetch_failed):
- # otherwise assume it was a LDST exception
- sync += pdecode2.ldst_exc.eq(ldst)
-
- with m.If(exec_pc_o_valid):
-
- # was this the last loop iteration?
- is_last = Signal()
- cur_vl = cur_state.svstate.vl
- comb += is_last.eq(next_srcstep == cur_vl)
-
- # return directly to Decode if Execute generated an
- # exception.
- with m.If(pdecode2.ldst_exc.happened):
- m.next = "DECODE_SV"
-
- # if MSR, PC or SVSTATE were changed by the previous
- # instruction, go directly back to Fetch, without
- # updating either MSR PC or SVSTATE
- with m.Elif(self.msr_changed | self.pc_changed |
- self.sv_changed):
- m.next = "ISSUE_START"
-
- # also return to Fetch, when no output was a vector
- # (regardless of SRCSTEP and VL), or when the last
- # instruction was really the last one of the VL loop
- with m.Elif((~pdecode2.loop_continue) | is_last):
- # before going back to fetch, update the PC state
- # register with the NIA.
- # ok here we are not reading the branch unit.
- # TODO: this just blithely overwrites whatever
- # pipeline updated the PC
- comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.i_data.eq(nia)
- # reset SRCSTEP before returning to Fetch
- if self.svp64_en:
- with m.If(pdecode2.loop_continue):
- comb += new_svstate.srcstep.eq(0)
- comb += new_svstate.dststep.eq(0)
- comb += update_svstate.eq(1)
- else:
- comb += new_svstate.srcstep.eq(0)
- comb += new_svstate.dststep.eq(0)
- comb += update_svstate.eq(1)
- m.next = "ISSUE_START"
-
- # returning to Execute? then, first update SRCSTEP
- with m.Else():
- comb += new_svstate.srcstep.eq(next_srcstep)
- comb += new_svstate.dststep.eq(next_dststep)
- comb += update_svstate.eq(1)
- # return to mask skip loop
- m.next = "PRED_SKIP"
-
- with m.Else():
- comb += dbg.core_stopped_i.eq(1)
- if flush_needed:
- # request the icache to stop asserting "failed"
- comb += core.icache.flush_in.eq(1)
- # stop instruction fault
- sync += pdecode2.instr_fault.eq(0)
+ # when using "single-step" mode, checking dbg.stopping_o
+ # prevents progress. allow execute to proceed once started
+ stopping = Const(0)
+ #if self.allow_overlap:
+ # stopping = dbg.stopping_o
+ with m.If(stopping):
+ # stopping: jump back to idle
+ m.next = "ISSUE_START"
if flush_needed:
# request the icache to stop asserting "failed"
comb += core.icache.flush_in.eq(1)
# stop instruction fault
sync += pdecode2.instr_fault.eq(0)
- # while stopped, allow updating the MSR, PC and SVSTATE
- with m.If(self.msr_i.ok):
- comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
- comb += self.state_w_msr.i_data.eq(self.msr_i.data)
- sync += self.msr_changed.eq(1)
- with m.If(self.pc_i.ok):
+ with m.Else():
+ comb += exec_insn_i_valid.eq(1) # trigger execute
+ with m.If(exec_insn_o_ready): # execute acknowledged us
+ m.next = "EXECUTE_WAIT"
+
+ with m.State("EXECUTE_WAIT"):
+ comb += exec_pc_i_ready.eq(1)
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=636
+ # the exception info needs to be blatted into
+ # pdecode.ldst_exc, and the instruction "re-run".
+ # when ldst_exc.happened is set, the PowerDecoder2
+ # reacts very differently: it re-writes the instruction
+ # with a "trap" (calls PowerDecoder2.trap()) which
+ # will *overwrite* whatever was requested and jump the
+ # PC to the exception address, as well as alter MSR.
+ # nothing else needs to be done other than to note
+ # the change of PC and MSR (and, later, SVSTATE)
+ with m.If(exc_happened):
+ mmu = core.fus.get_exc("mmu0")
+ ldst = core.fus.get_exc("ldst0")
+ if mmu is not None:
+ with m.If(fetch_failed):
+ # instruction fetch: exception is from MMU
+ # reset instr_fault (highest priority)
+ sync += pdecode2.ldst_exc.eq(mmu)
+ sync += pdecode2.instr_fault.eq(0)
+ if flush_needed:
+ # request icache to stop asserting "failed"
+ comb += core.icache.flush_in.eq(1)
+ with m.If(~fetch_failed):
+ # otherwise assume it was a LDST exception
+ sync += pdecode2.ldst_exc.eq(ldst)
+
+ with m.If(exec_pc_o_valid):
+
+ # was this the last loop iteration?
+ is_last = Signal()
+ cur_vl = cur_state.svstate.vl
+ comb += is_last.eq(next_srcstep == cur_vl)
+
+ with m.If(pdecode2.instr_fault):
+ # reset instruction fault, try again
+ sync += pdecode2.instr_fault.eq(0)
+ m.next = "ISSUE_START"
+
+ # return directly to Decode if Execute generated an
+ # exception.
+ with m.Elif(pdecode2.ldst_exc.happened):
+ m.next = "DECODE_SV"
+
+ # if MSR, PC or SVSTATE were changed by the previous
+ # instruction, go directly back to Fetch, without
+ # updating either MSR PC or SVSTATE
+ with m.Elif(self.msr_changed | self.pc_changed |
+ self.sv_changed):
+ m.next = "ISSUE_START"
+
+ # also return to Fetch, when no output was a vector
+ # (regardless of SRCSTEP and VL), or when the last
+ # instruction was really the last one of the VL loop
+ with m.Elif((~pdecode2.loop_continue) | is_last):
+ # before going back to fetch, update the PC state
+ # register with the NIA.
+ # ok here we are not reading the branch unit.
+ # TODO: this just blithely overwrites whatever
+ # pipeline updated the PC
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.i_data.eq(self.pc_i.data)
- sync += self.pc_changed.eq(1)
- with m.If(self.svstate_i.ok):
- comb += new_svstate.eq(self.svstate_i.data)
- comb += update_svstate.eq(1)
- sync += self.sv_changed.eq(1)
+ comb += self.state_w_pc.i_data.eq(nia)
+ # reset SRCSTEP before returning to Fetch
+ if self.svp64_en:
+ with m.If(pdecode2.loop_continue):
+ comb += new_svstate.srcstep.eq(0)
+ comb += new_svstate.dststep.eq(0)
+ comb += self.update_svstate.eq(1)
+ else:
+ comb += new_svstate.srcstep.eq(0)
+ comb += new_svstate.dststep.eq(0)
+ comb += self.update_svstate.eq(1)
+ m.next = "ISSUE_START"
+
+ # returning to Execute? then, first update SRCSTEP
+ with m.Else():
+ comb += new_svstate.srcstep.eq(next_srcstep)
+ comb += new_svstate.dststep.eq(next_dststep)
+ comb += self.update_svstate.eq(1)
+ # return to mask skip loop
+ m.next = "PRED_SKIP"
+
# check if svstate needs updating: if so, write it to State Regfile
- with m.If(update_svstate):
- comb += self.state_w_sv.wen.eq(1 << StateRegs.SVSTATE)
- comb += self.state_w_sv.i_data.eq(new_svstate)
- sync += cur_state.svstate.eq(new_svstate) # for next clock
+ with m.If(self.update_svstate):
+ sync += cur_state.svstate.eq(self.new_svstate) # for next clock
def execute_fsm(self, m, core,
exec_insn_i_valid, exec_insn_o_ready,
comb = m.d.comb
sync = m.d.sync
+ dbg = self.dbg
pdecode2 = self.pdecode2
# temporaries
# there were *TWO* instructions:
# 1) the failed LDST 2) a TRAP.
with m.If(~pdecode2.ldst_exc.happened &
- ~fetch_failed):
+ ~pdecode2.instr_fault):
comb += self.insn_done.eq(1)
m.next = "INSN_START" # back to fetch
+ # terminate returns directly to INSN_START
+ with m.If(dbg.terminate_i):
+ # comb += self.insn_done.eq(1) - no because it's not
+ m.next = "INSN_START" # back to fetch
def elaborate(self, platform):
m = super().elaborate(platform)
nia = Signal(64)
# connect up debug signals
- comb += dbg.terminate_i.eq(core.o.core_terminate_o)
+ with m.If(core.o.core_terminate_o):
+ comb += dbg.terminate_i.eq(1)
# pass the prefix mode from Fetch to Issue, so the latter can loop
# on VL==0
self.ti = TestIssuerInternal(pspec)
self.pll = DummyPLL(instance=True)
+ self.dbg_rst_i = Signal(reset_less=True)
+
# PLL direct clock or not
self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
if self.pll_en:
# internal clock is set to selector clock-out. has the side-effect of
# running TestIssuer at this speed (see DomainRenamer("intclk") above)
# debug clock runs at coresync internal clock
- cd_coresync = ClockDomain("coresync")
- #m.domains += cd_coresync
if self.ti.dbg_domain != 'sync':
cd_dbgsync = ClockDomain("dbgsync")
- #m.domains += cd_dbgsync
- intclk = ClockSignal("coresync")
+ intclk = ClockSignal(self.ti.core_domain)
dbgclk = ClockSignal(self.ti.dbg_domain)
# XXX BYPASS PLL XXX
# XXX BYPASS PLL XXX
# XXX BYPASS PLL XXX
if self.pll_en:
comb += intclk.eq(self.ref_clk)
+ assert self.ti.core_domain != 'sync', \
+ "cannot set core_domain to sync and use pll at the same time"
else:
- comb += intclk.eq(ClockSignal())
+ if self.ti.core_domain != 'sync':
+ comb += intclk.eq(ClockSignal())
if self.ti.dbg_domain != 'sync':
dbgclk = ClockSignal(self.ti.dbg_domain)
comb += dbgclk.eq(intclk)
+ comb += self.ti.dbg_rst_i.eq(self.dbg_rst_i)
return m
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