add div FSM as default for test_issuer in verilog and ilang gen

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3d168da674490010dd2ead87d30f3f1456f6ab6c..168f389f0d57c4800e99c07f6218683607ac9011 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -260,6 +260,7 @@ class TestIssuer(Elaboratable):
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',