add div FSM as default for test_issuer in verilog and ilang gen

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index d77464b545d20da905f319e1c4f379cd9ec35d5b..90b8308131766e5f651ea321d948ef9992dbcee1 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -11,6 +11,7 @@ from soc.simple.issuer import TestIssuer
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',