add "nocore" option to build verilog

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 820e5fd32ddfb3603efcd53b0639d1eb22080ff7..eec494af0094ff170318ab2afa8ff915f662ead1 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,6 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
+                         nocore=True, # to help test coriolis2 ioring
                          gpio=False, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)