# set to 32 to make data wishbone bus 32-bit
#wb_data_wid=32,
xics=True,
- gpio=True, # for test purposes
+ nocore=True, # to help test coriolis2 ioring
+ gpio=False, # for test purposes
+ debug="jtag", # set to jtag or dmi
units=units)
+
dut = TestIssuer(pspec)
vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")