add "nocore" option to build verilog

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 9ba52fe628d531f1170739caf464768827d45ac7..eec494af0094ff170318ab2afa8ff915f662ead1 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -25,7 +25,14 @@ if __name__ == '__main__':
                          reg_wid=64,
                          # set to 32 for instruction-memory width=32
                          imem_reg_wid=64,
+                         # set to 32 to make data wishbone bus 32-bit
+                         #wb_data_wid=32,
+                         xics=True,
+                         nocore=True, # to help test coriolis2 ioring
+                         gpio=False, # for test purposes
+                         debug="jtag", # set to jtag or dmi
                          units=units)
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")