big rename, global/search/replace of ready_o with o_ready and the other

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 0bf1ee42d019ef594df0333e025a2bf7b0371030..2edb84c605963a9bdd7deff78ad00d7e9752f0a3 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -9,19 +9,23 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
-from soc.decoder.isa.caller import special_sprs
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.isa.all import ISA
-from soc.decoder.power_enums import SPR, spr_dict, Function, XER_bits
+from openpower.decoder.isa.caller import special_sprs
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import PowerDecode2
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.isa.all import ISA
+
+# note that using SPRreduced has to be done to match the
+# PowerDecoder2 SPR map
+from openpower.decoder.power_enums import SPRreduced as SPR
+from openpower.decoder.power_enums import spr_dict, Function, XER_bits
 from soc.config.test.test_loadstore import TestMemPspec
-from soc.config.endian import bigendian
+from openpower.endian import bigendian
 
 from soc.simple.core import NonProductionCore
 from soc.experiment.compalu_multi import find_ok  # hack
 
-from soc.fu.compunits.test.test_compunit import (setup_test_memory,
+from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
                                                  check_sim_memory)
 
 # test with ALU data and Logical data
@@ -31,8 +35,19 @@ from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 from soc.fu.cr.test.test_pipe_caller import CRTestCase
 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
-from soc.regfile.util import spr_to_fast_reg
+from openpower.util import spr_to_fast_reg
 
+# list of SPRs that are controlled and managed by the MMU
+mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
+
+def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
+        fsm = core.fus.get_fu("mmu0").alu
+        yield fsm.mmu.l_in.mtspr.eq(1)
+        yield fsm.mmu.l_in.sprn.eq(i)
+        yield fsm.mmu.l_in.rs.eq(val)
+        yield
+        yield fsm.mmu.l_in.mtspr.eq(0)
+        print("mmu_spr was updated")
 
 def setup_regs(pdecode2, core, test):
 
@@ -102,11 +117,18 @@ def setup_regs(pdecode2, core, test):
                 if sprname == x.name:
                     print("setting slow SPR %d (%s) to %x" %
                           (i, sprname, val))
-                    yield sregs.memory._array[i].eq(val)
+                    if not sprname in mmu_sprs:
+                        yield sregs.memory._array[i].eq(val)
+                    else:
+                        yield from set_mmu_spr(sprname, i, val, core)
         else:
-            yield fregs.regs[fast].reg.eq(val)
             print("setting fast reg %d (%s) to %x" %
                   (fast, sprname, val))
+            if fregs.unary:
+                rval = fregs.int.regs[fast].reg
+            else:
+                rval = fregs.memory._array[fast]
+            yield rval.eq(val)
 
     # allow changes to settle before reporting on XER
     yield Settle()
@@ -135,7 +157,8 @@ def check_regs(dut, sim, core, test, code):
     for i in range(32):
         simregval = sim.gpr[i].asint()
         dut.assertEqual(simregval, intregs[i],
-                        "int reg %d not equal %s" % (i, repr(code)))
+                        "int reg %d not equal %s. got %x expected %x" % \
+                            (i, repr(code), simregval, intregs[i]))
 
     # CRs
     crregs = []
@@ -217,7 +240,7 @@ class TestRunner(FHDLTestCase):
         m = Module()
         comb = m.d.comb
         instruction = Signal(32)
-        ivalid_i = Signal()
+        ii_valid = Signal()
 
         pspec = TestMemPspec(ldst_ifacetype='testpi',
                              imem_ifacetype='',
@@ -230,7 +253,7 @@ class TestRunner(FHDLTestCase):
         l0 = core.l0
 
         comb += core.raw_opcode_i.eq(instruction)
-        comb += core.ivalid_i.eq(ivalid_i)
+        comb += core.ii_valid.eq(ii_valid)
 
         # temporary hack: says "go" immediately for both address gen and ST
         ldst = core.fus.fus['ldst0']
@@ -255,7 +278,7 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
-                yield from setup_test_memory(l0, sim)
+                yield from setup_tst_memory(l0, sim)
                 yield from setup_regs(core, test)
 
                 index = sim.pc.CIA.value//4
@@ -268,7 +291,7 @@ class TestRunner(FHDLTestCase):
                     # ask the decoder to decode this binary data (endian'd)
                     yield core.bigendian_i.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
-                    yield ivalid_i.eq(1)
+                    yield ii_valid.eq(1)
                     yield Settle()
                     # fn_unit = yield pdecode2.e.fn_unit
                     #fuval = self.funit.value
@@ -279,7 +302,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
                     yield from wait_for_busy_clear(core)
-                    yield ivalid_i.eq(0)
+                    yield ii_valid.eq(0)
                     yield
 
                     print("sim", code)