big rename, global/search/replace of ready_o with o_ready and the other

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index bb8cb93dd8edcd5701170b55302687bdb6cef1fe..2edb84c605963a9bdd7deff78ad00d7e9752f0a3 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -25,7 +25,7 @@ from openpower.endian import bigendian
 from soc.simple.core import NonProductionCore
 from soc.experiment.compalu_multi import find_ok  # hack
 
-from soc.fu.compunits.test.test_compunit import (setup_test_memory,
+from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
                                                  check_sim_memory)
 
 # test with ALU data and Logical data
@@ -41,7 +41,7 @@ from openpower.util import spr_to_fast_reg
 mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
 
 def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
-        fsm = core.fus.fus["mmu0"].alu
+        fsm = core.fus.get_fu("mmu0").alu
         yield fsm.mmu.l_in.mtspr.eq(1)
         yield fsm.mmu.l_in.sprn.eq(i)
         yield fsm.mmu.l_in.rs.eq(val)
@@ -240,7 +240,7 @@ class TestRunner(FHDLTestCase):
         m = Module()
         comb = m.d.comb
         instruction = Signal(32)
-        ivalid_i = Signal()
+        ii_valid = Signal()
 
         pspec = TestMemPspec(ldst_ifacetype='testpi',
                              imem_ifacetype='',
@@ -253,7 +253,7 @@ class TestRunner(FHDLTestCase):
         l0 = core.l0
 
         comb += core.raw_opcode_i.eq(instruction)
-        comb += core.ivalid_i.eq(ivalid_i)
+        comb += core.ii_valid.eq(ii_valid)
 
         # temporary hack: says "go" immediately for both address gen and ST
         ldst = core.fus.fus['ldst0']
@@ -278,7 +278,7 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
-                yield from setup_test_memory(l0, sim)
+                yield from setup_tst_memory(l0, sim)
                 yield from setup_regs(core, test)
 
                 index = sim.pc.CIA.value//4
@@ -291,7 +291,7 @@ class TestRunner(FHDLTestCase):
                     # ask the decoder to decode this binary data (endian'd)
                     yield core.bigendian_i.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
-                    yield ivalid_i.eq(1)
+                    yield ii_valid.eq(1)
                     yield Settle()
                     # fn_unit = yield pdecode2.e.fn_unit
                     #fuval = self.funit.value
@@ -302,7 +302,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
                     yield from wait_for_busy_clear(core)
-                    yield ivalid_i.eq(0)
+                    yield ii_valid.eq(0)
                     yield
 
                     print("sim", code)