from soc.simple.test.test_core import (setup_regs, check_regs,
wait_for_busy_clear,
wait_for_busy_hi)
-from soc.fu.compunits.test.test_compunit import (setup_test_memory,
+from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
check_sim_memory)
from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
from nmutil.util import wrap
counter = 0 # test to pause/start
yield from setup_i_memory(imem, pc, instructions)
- yield from setup_test_memory(l0, sim)
+ yield from setup_tst_memory(l0, sim)
yield from setup_regs(pdecode2, core, test)
# set PC and SVSTATE
initial_svstate = test.svstate
if isinstance(initial_svstate, int):
initial_svstate = SVP64State(initial_svstate)
- yield svstate_i.eq(initial_svstate.spr.value)
+ yield svstate_i.eq(initial_svstate.value)
yield issuer.svstate_i.ok.eq(1)
yield
traces = [
'clk',
('state machines', 'closed', [
- 'fetch_pc_valid_i', 'fetch_pc_ready_o',
+ 'fetch_pc_i_valid', 'fetch_pc_o_ready',
'fetch_fsm_state',
- 'fetch_insn_valid_o', 'fetch_insn_ready_i',
- 'pred_insn_valid_i', 'pred_insn_ready_o',
+ 'fetch_insn_o_valid', 'fetch_insn_i_ready',
+ 'pred_insn_i_valid', 'pred_insn_o_ready',
'fetch_predicate_state',
- 'pred_mask_valid_o', 'pred_mask_ready_i',
+ 'pred_mask_o_valid', 'pred_mask_i_ready',
'issue_fsm_state',
- 'exec_insn_valid_i', 'exec_insn_ready_o',
+ 'exec_insn_i_valid', 'exec_insn_o_ready',
'exec_fsm_state',
- 'exec_pc_valid_o', 'exec_pc_ready_i',
+ 'exec_pc_o_valid', 'exec_pc_i_ready',
'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
'is_last', 'dec2.no_out_vec']),
{'comment': 'fetch and decode'},
'core.int.rp_src1.memory(7)[63:0]',
'core.int.rp_src1.memory(9)[63:0]',
'core.int.rp_src1.memory(10)[63:0]',
- 'core.int.rp_src1.memory(13)[63:0]',
- {'comment': 'memory port interface'},
- 'core.l0.pimem.ldst_port0_is_ld_i',
- 'core.l0.pimem.ldst_port0_is_st_i',
- 'core.l0.pimem.ldst_port0_busy_o',
- 'core.l0.pimem.ldst_port0_addr_i[47:0]',
- 'core.l0.pimem.ldst_port0_addr_i_ok',
- 'core.l0.pimem.ldst_port0_addr_ok_o',
- 'core.l0.pimem.ldst_port0_st_data_i[63:0]',
- 'core.l0.pimem.ldst_port0_st_data_i_ok',
- 'core.l0.pimem.ldst_port0_ld_data_o[63:0]',
- 'core.l0.pimem.ldst_port0_ld_data_o_ok'
+ 'core.int.rp_src1.memory(13)[63:0]'
]
+ # PortInterface module path varies depending on MMU option
+ if self.microwatt_mmu:
+ pi_module = 'core.ldst0'
+ else:
+ pi_module = 'core.fus.ldst0'
+
+ traces += [('ld/st port interface', {'submodule': pi_module}, [
+ 'oper_r__insn_type',
+ 'ldst_port0_is_ld_i',
+ 'ldst_port0_is_st_i',
+ 'ldst_port0_busy_o',
+ 'ldst_port0_addr_i[47:0]',
+ 'ldst_port0_addr_i_ok',
+ 'ldst_port0_addr_ok_o',
+ 'ldst_port0_exc_happened',
+ 'ldst_port0_st_data_i[63:0]',
+ 'ldst_port0_st_data_i_ok',
+ 'ldst_port0_ld_data_o[63:0]',
+ 'ldst_port0_ld_data_o_ok',
+ 'exc_o_happened',
+ 'cancel'
+ ])]
+
if self.microwatt_mmu:
traces += [
{'comment': 'microwatt_mmu'},