Adjust PortInterface traces according to MMU option

[soc.git] / src / soc / simple / test / test_runner.py

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 85afa3092ac599eae6b93362070b1badffd36356..fd3f15c386045150ee738df9de6a9003be1de575 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -28,7 +28,7 @@ from soc.config.test.test_loadstore import TestMemPspec
 from soc.simple.test.test_core import (setup_regs, check_regs,
                                        wait_for_busy_clear,
                                        wait_for_busy_hi)
-from soc.fu.compunits.test.test_compunit import (setup_test_memory,
+from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
                                                  check_sim_memory)
 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
 from nmutil.util import wrap
@@ -134,7 +134,7 @@ class TestRunner(FHDLTestCase):
         m = Module()
         comb = m.d.comb
         pc_i = Signal(32)
-        svstate_i = Signal(32)
+        svstate_i = Signal(64)
 
         if self.microwatt_mmu:
             ldst_ifacetype = 'test_mmu_cache_wb'
@@ -230,7 +230,7 @@ class TestRunner(FHDLTestCase):
                     counter = 0  # test to pause/start
 
                     yield from setup_i_memory(imem, pc, instructions)
-                    yield from setup_test_memory(l0, sim)
+                    yield from setup_tst_memory(l0, sim)
                     yield from setup_regs(pdecode2, core, test)
 
                     # set PC and SVSTATE
@@ -240,7 +240,7 @@ class TestRunner(FHDLTestCase):
                     initial_svstate = test.svstate
                     if isinstance(initial_svstate, int):
                         initial_svstate = SVP64State(initial_svstate)
-                    yield svstate_i.eq(initial_svstate.spr.value)
+                    yield svstate_i.eq(initial_svstate.value)
                     yield issuer.svstate_i.ok.eq(1)
                     yield
 
@@ -412,20 +412,32 @@ class TestRunner(FHDLTestCase):
             'core.int.rp_src1.memory(7)[63:0]',
             'core.int.rp_src1.memory(9)[63:0]',
             'core.int.rp_src1.memory(10)[63:0]',
-            'core.int.rp_src1.memory(13)[63:0]',
-            {'comment': 'memory port interface'},
-            'core.l0.pimem.ldst_port0_is_ld_i',
-            'core.l0.pimem.ldst_port0_is_st_i',
-            'core.l0.pimem.ldst_port0_busy_o',
-            'core.l0.pimem.ldst_port0_addr_i[47:0]',
-            'core.l0.pimem.ldst_port0_addr_i_ok',
-            'core.l0.pimem.ldst_port0_addr_ok_o',
-            'core.l0.pimem.ldst_port0_st_data_i[63:0]',
-            'core.l0.pimem.ldst_port0_st_data_i_ok',
-            'core.l0.pimem.ldst_port0_ld_data_o[63:0]',
-            'core.l0.pimem.ldst_port0_ld_data_o_ok'
+            'core.int.rp_src1.memory(13)[63:0]'
         ]
 
+        # PortInterface module path varies depending on MMU option
+        if self.microwatt_mmu:
+            pi_module = 'core.ldst0'
+        else:
+            pi_module = 'core.fus.ldst0'
+
+        traces += [('ld/st port interface', {'submodule': pi_module}, [
+            'oper_r__insn_type',
+            'ldst_port0_is_ld_i',
+            'ldst_port0_is_st_i',
+            'ldst_port0_busy_o',
+            'ldst_port0_addr_i[47:0]',
+            'ldst_port0_addr_i_ok',
+            'ldst_port0_addr_ok_o',
+            'ldst_port0_exc_happened',
+            'ldst_port0_st_data_i[63:0]',
+            'ldst_port0_st_data_i_ok',
+            'ldst_port0_ld_data_o[63:0]',
+            'ldst_port0_ld_data_o_ok',
+            'exc_o_happened',
+            'cancel'
+        ])]
+
         if self.microwatt_mmu:
             traces += [
                 {'comment': 'microwatt_mmu'},