rename invert_a to invert_in because logical inverts RB

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index c5c2094527aa417945475d737ac7a93fd699f3e0..b3e6c691dfa743cd9f235453bebd9200d309a4a7 100644 (file)
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -42,7 +42,7 @@ class Decode2ToOperand(RecordObject):
         self.lk = Signal(reset_less=True)
         self.rc = Data(1, "rc")
         self.oe = Data(1, "oe")
-        self.invert_a = Signal(reset_less=True)
+        self.invert_in = Signal(reset_less=True)
         self.zero_a = Signal(reset_less=True)
         self.input_carry = Signal(CryIn, reset_less=True)
         self.output_carry = Signal(reset_less=True)

diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py
index 195044738bd693777a00b025e65e16d6d356eaf2..b7ac61f708ff3bfab70150e7a422b9366d710b8e 100644 (file)
--- a/src/soc/decoder/formal/proof_decoder2.py
+++ b/src/soc/decoder/formal/proof_decoder2.py
@@ -182,7 +182,7 @@ class Driver(Elaboratable):
         pdecode2 = m.submodules.pdecode2
         dec = pdecode2.dec
         e = pdecode2.e
-        comb += Assert(e.invert_a == dec.op.inv_a)
+        comb += Assert(e.invert_in == dec.op.inv_a)
         comb += Assert(e.invert_out == dec.op.inv_out)
         comb += Assert(e.input_carry == dec.op.cry_in)
         comb += Assert(e.output_carry == dec.op.cry_out)

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 31ef345095018c5ed75b16f92eedf48e78300a8a..e3d349bb57f0a1638d987d018a08596b1b2f6c74 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -406,7 +406,7 @@ class ISACaller:
         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 
     def handle_carry_(self, inputs, outputs, already_done):
-        inv_a = yield self.dec2.e.do.invert_a
+        inv_a = yield self.dec2.e.do.invert_in
         if inv_a:
             inputs[0] = ~inputs[0]
 
@@ -442,7 +442,7 @@ class ISACaller:
             self.spr['XER'][XER_bits['CA32']] = cy32
 
     def handle_overflow(self, inputs, outputs, div_overflow):
-        inv_a = yield self.dec2.e.do.invert_a
+        inv_a = yield self.dec2.e.do.invert_in
         if inv_a:
             inputs[0] = ~inputs[0]
 

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 838cb121197db57bffe58e28ab02c50e5a1d57fb..51c3511f9dc93cde787029b4903e1358f57594da 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -671,7 +671,7 @@ class PowerDecode2(Elaboratable):
 
         # decoded/selected instruction flags
         comb += do.data_len.eq(op.ldst_len)
-        comb += do.invert_a.eq(op.inv_a)
+        comb += do.invert_in.eq(op.inv_a)
         comb += do.invert_out.eq(op.inv_out)
         comb += do.input_carry.eq(op.cry_in)   # carry comes in
         comb += do.output_carry.eq(op.cry_out)  # carry goes out

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 59bca26e358051b9579a9686833c8a9c93a1e393..9c8115ce69da2c035f0d674ac3768fceb415020d 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -26,14 +26,14 @@ import operator
 
 class Adder(Elaboratable):
     def __init__(self, width):
-        self.invert_a = Signal()
+        self.invert_in = Signal()
         self.a = Signal(width)
         self.b = Signal(width)
         self.o = Signal(width, name="add_o")
 
     def elaborate(self, platform):
         m = Module()
-        with m.If(self.invert_a):
+        with m.If(self.invert_in):
             m.d.comb += self.o.eq((~self.a) + self.b)
         with m.Else():
             m.d.comb += self.o.eq(self.a + self.b)
@@ -206,7 +206,7 @@ class ALU(Elaboratable):
             ]
 
         # pass invert (and carry later)
-        m.d.comb += add.invert_a.eq(self.op.invert_a)
+        m.d.comb += add.invert_in.eq(self.op.invert_in)
 
         go_now = Signal(reset_less=True)  # testing no-delay ALU
 
@@ -390,7 +390,7 @@ def run_op(dut, a, b, op, inv_a=0):
     yield dut.a.eq(a)
     yield dut.b.eq(b)
     yield dut.op.insn_type.eq(op)
-    yield dut.op.invert_a.eq(inv_a)
+    yield dut.op.invert_in.eq(inv_a)
     yield dut.n.ready_i.eq(0)
     yield dut.p.valid_i.eq(1)
     yield dut.n.ready_i.eq(1)
@@ -404,7 +404,7 @@ def run_op(dut, a, b, op, inv_a=0):
     yield dut.a.eq(0)
     yield dut.b.eq(0)
     yield dut.op.insn_type.eq(0)
-    yield dut.op.invert_a.eq(0)
+    yield dut.op.invert_in.eq(0)
 
     # wait for the ALU to present the output data
     while not (yield dut.n.valid_o):
@@ -462,7 +462,7 @@ def test_alu_parallel():
         yield dut.a.eq(a)
         yield dut.b.eq(b)
         yield dut.op.insn_type.eq(op)
-        yield dut.op.invert_a.eq(inv_a)
+        yield dut.op.invert_in.eq(inv_a)
         yield dut.p.valid_i.eq(1)
         yield
         # wait for ready_o to be asserted
@@ -475,7 +475,7 @@ def test_alu_parallel():
         yield dut.a.eq(0)
         yield dut.b.eq(0)
         yield dut.op.insn_type.eq(0)
-        yield dut.op.invert_a.eq(0)
+        yield dut.op.invert_in.eq(0)
 
     def receive():
         # signal readiness to receive data

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index dcab911aa657e5f2fada58e6e207b85ef737c9f8..89d2da1a2c8c0210b0733d6a9c5b0f2ef634b92c 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -175,7 +175,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
     yield dut.src1_i.eq(a)
     yield dut.src2_i.eq(b)
     yield dut.oper_i.insn_type.eq(op)
-    yield dut.oper_i.invert_a.eq(inv_a)
+    yield dut.oper_i.invert_in.eq(inv_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.issue_i.eq(1)

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 69269353ea5c056fb3d21d17ab4ebea88e86a5fd..97eb635f2f2c59d6a722c898b2bd6a3ac49a26a2 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -77,7 +77,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
     yield dut.src_i[0].eq(a)
     yield dut.src_i[1].eq(b)
     yield dut.oper_i.insn_type.eq(op)
-    yield dut.oper_i.invert_a.eq(inv_a)
+    yield dut.oper_i.invert_in.eq(inv_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.oper_i.zero_a.eq(zero_a)
@@ -285,7 +285,7 @@ class CompUnitParallelTest:
 
         # at the same time, present the operation
         yield self.dut.oper_i.insn_type.eq(self.op)
-        yield self.dut.oper_i.invert_a.eq(self.inv_a)
+        yield self.dut.oper_i.invert_in.eq(self.inv_a)
         yield self.dut.oper_i.imm_data.imm.eq(self.imm)
         yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
         yield self.dut.oper_i.zero_a.eq(self.zero_a)
@@ -310,7 +310,7 @@ class CompUnitParallelTest:
         # note: rdmaskn must be held, while busy_o is active
         # TODO: deactivate rdmaskn when the busy_o cycle ends
         yield self.dut.oper_i.insn_type.eq(0)
-        yield self.dut.oper_i.invert_a.eq(0)
+        yield self.dut.oper_i.invert_in.eq(0)
         yield self.dut.oper_i.imm_data.imm.eq(0)
         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
         yield self.dut.oper_i.zero_a.eq(0)

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 0b231cfda868e1a2565282bbd4bd4b4333aa6fbd..07fdb5f716e7beb3f9fa384060f846298c82b12b 100644 (file)
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -16,7 +16,7 @@ class CompALUOpSubset(CompOpSubsetBase):
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
-                  ('invert_a', 1),
+                  ('invert_in', 1),
                   ('zero_a', 1),
                   ('invert_out', 1),
                   ('write_cr0', 1),

diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py
index 0d664a750c872915ab421f58f6173088b48a0b79..afa39b1319b54c42134f55d7409efb46280c1642 100644 (file)
--- a/src/soc/fu/alu/formal/proof_input_stage.py
+++ b/src/soc/fu/alu/formal/proof_input_stage.py
@@ -51,7 +51,7 @@ class Driver(Elaboratable):
             dut_sig = getattr(dut.o.ctx.op, name)
             comb += Assert(dut_sig == rec_sig)
 
-        with m.If(rec.invert_a):
+        with m.If(rec.invert_in):
             comb += Assert(dut.o.a == ~a)
         with m.Else():
             comb += Assert(dut.o.a == a)

diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py
index 52409c4ea6617c59df754481381f6c23a28d0137..89346e21526ef1f3bd65f6fc9dcef660a5047a27 100644 (file)
--- a/src/soc/fu/branch/formal/proof_input_stage.py
+++ b/src/soc/fu/branch/formal/proof_input_stage.py
@@ -51,7 +51,7 @@ class Driver(Elaboratable):
             dut_sig = getattr(dut.o.ctx.op, name)
             comb += Assert(dut_sig == rec_sig)
 
-        with m.If(rec.invert_a):
+        with m.If(rec.invert_in):
             comb += Assert(dut.o.a == ~a)
         with m.Else():
             comb += Assert(dut.o.a == a)

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 1b64e5ce295342b760564d7764cd511192bbda85..238c8d57a9dec7907d497701597f01e419d90ebb 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -23,8 +23,8 @@ class CommonInputStage(PipeModBase):
         if hasattr(self, "invert_op"):
             op_to_invert = self.invert_op
 
-        if hasattr(op, "invert_a") and op_to_invert == 'ra':
-            with m.If(op.invert_a):
+        if hasattr(op, "invert_in") and op_to_invert == 'ra':
+            with m.If(op.invert_in):
                 comb += a.eq(~self.i.a)
             with m.Else():
                 comb += a.eq(self.i.a)
@@ -38,8 +38,8 @@ class CommonInputStage(PipeModBase):
         # operand b to be as-is or inverted
         b = Signal.like(self.i.b)
 
-        if hasattr(op, "invert_a") and op_to_invert == 'rb':
-            with m.If(op.invert_a):
+        if hasattr(op, "invert_in") and op_to_invert == 'rb':
+            with m.If(op.invert_in):
                 comb += b.eq(~self.i.b)
             with m.Else():
                 comb += b.eq(self.i.b)

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index ab6e392e75061862365c331d05acecb84d7b5406..ed0c75119326f54c553b16c627e753f229a9e7ea 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -51,7 +51,7 @@ class Driver(Elaboratable):
             dut_sig = getattr(dut.o.ctx.op, name)
             comb += Assert(dut_sig == rec_sig)
 
-        with m.If(rec.invert_a):
+        with m.If(rec.invert_in):
             comb += Assert(dut.o.a == ~a)
         with m.Else():
             comb += Assert(dut.o.a == a)

diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py
index 3e6780382c1f17a8790ec1ec49c46d36aa13a528..ad30488adcf7b55a0dcef959ac9355a005455316 100644 (file)
--- a/src/soc/fu/logical/logical_input_record.py
+++ b/src/soc/fu/logical/logical_input_record.py
@@ -16,7 +16,7 @@ class CompLogicalOpSubset(CompOpSubsetBase):
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
-                  ('invert_a', 1),
+                  ('invert_in', 1),
                   ('zero_a', 1),
                   ('input_carry', CryIn),
                   ('invert_out', 1),

diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py
index b5334decae4768c63bae93c18672533bf6b3c9c2..6e1683711637fe6a3d83574a0a8d54c54b410803 100644 (file)
--- a/src/soc/fu/mul/mul_input_record.py
+++ b/src/soc/fu/mul/mul_input_record.py
@@ -17,7 +17,7 @@ class CompMULOpSubset(CompOpSubsetBase):
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
-                  ('invert_a', 1),
+                  ('invert_in', 1),
                   ('zero_a', 1),
                   ('invert_out', 1),
                   ('write_cr0', 1),