periphery: peripherals now in coreplex (#26)

* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 204f76782e13ad157c555163e0467e0aab941f1c..109ffb82991df1dcea50c16d013624b5f81373fb 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -3,19 +3,18 @@ package sifive.blocks.devices.gpio
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
 import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
-trait HasPeripheryGPIO extends HasSystemNetworks {
+trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
   val gpioParams = p(PeripheryGPIOKey)
-  val gpio = gpioParams map {params =>
-    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
-    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := gpio.intnode
+  val gpio = gpioParams map { params =>
+    val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
+    gpio.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := gpio.intnode
     gpio
   }
 }

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 94bbadd886d24e131c0876945a3e6ecb327ec9ad..1cc927f46adf7b5243c76d31c23c0f703e4ac295 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -3,18 +3,17 @@ package sifive.blocks.devices.i2c
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.{HasSystemNetworks}
-import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 
 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
 
-trait HasPeripheryI2C extends HasSystemNetworks {
+trait HasPeripheryI2C extends HasPeripheryBus {
   val i2cParams = p(PeripheryI2CKey)
   val i2c = i2cParams map { params =>
-    val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
-    i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := i2c.intnode
+    val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
+    i2c.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := i2c.intnode
     i2c
   }
 }

diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index 240f89bef173dab65b3d053c9eeab8c0f9633052..8b6303e2ffb32f03abe1e8cecfe88aef2548216c 100644 (file)
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -3,22 +3,25 @@ package sifive.blocks.devices.mockaon
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.devices.debug.HasPeripheryDebug
+import freechips.rocketchip.devices.tilelink.HasPeripheryClint
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
-import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter}
+import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
 import freechips.rocketchip.util.ResetCatchAndSync
 
 case object PeripheryMockAONKey extends Field[MockAONParams]
 
-trait HasPeripheryMockAON extends HasSystemNetworks with HasCoreplexRISCVPlatform {
+trait HasPeripheryMockAON extends HasPeripheryBus
+    with HasInterruptBus
+    with HasPeripheryClint
+    with HasPeripheryDebug {
   // We override the clock & Reset here so that all synchronizers, etc
   // are in the proper clock domain.
   val mockAONParams= p(PeripheryMockAONKey)
-  val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
-  val aon_int = LazyModule(new IntXing)
-  aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
-  aon_int.intnode := aon.intnode
-  intBus.intnode := aon_int.intnode
+  val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
+  aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
+  ibus.fromAsync := aon.intnode
 }
 
 trait HasPeripheryMockAONBundle {
@@ -39,7 +42,7 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
   outer.aon.module.clock := Bool(false).asClock
   outer.aon.module.reset := Bool(true)
 
-  outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool
+  outer.clint.module.io.rtcTick := outer.aon.module.io.rtc.asUInt.toBool
 
-  outer.aon.module.io.ndreset := outer.coreplex.module.io.ndreset
+  outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
 }

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index ea17f8a572d46cbe0b0812666cdd993b34c440c3..5ff9ccfe8f5b23dc17c79886c6afd2722a493070 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -3,11 +3,9 @@ package sifive.blocks.devices.pwm
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
-
 import sifive.blocks.devices.gpio._
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
@@ -30,12 +28,12 @@ class PWMGPIOPort(val c: PWMParams) extends Module {
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
   val pwmParams = p(PeripheryPWMKey)
   val pwms = pwmParams map { params =>
-    val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
-    pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := pwm.intnode
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+    pwm.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := pwm.intnode
     pwm
   }
 }

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 15e28faf302ea5727947ef7350872f3f67f8fa6e..37151bd06cda84a0e8a5f6b9178824418c024e64 100644 (file)
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -3,19 +3,19 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.tilelink.{TLFragmenter}
 import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasSystemNetworks {
+trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
   val spiParams = p(PeripherySPIKey)  
   val spis = spiParams map { params =>
-    val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
-    spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := spi.intnode
+    val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
+    spi.rnode := pbus.toVariableWidthSlaves
+    ibus.fromSync := spi.intnode
     spi
   }
 }
@@ -41,13 +41,13 @@ trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPI
 
 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasSystemNetworks {
+trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
   val spiFlashParams = p(PeripherySPIFlashKey)  
   val qspi = spiFlashParams map { params =>
-    val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
-    qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-    intBus.intnode := qspi.intnode
+    val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+    qspi.rnode := pbus.toVariableWidthSlaves
+    qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+    ibus.fromSync := qspi.intnode
     qspi
   }
 }
@@ -73,4 +73,3 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe
     io <> device.module.io.port
   }
 }
-

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 5732fd904b3df492f76e17dd1d4f6280708d5646..1a19be8eb03b94f68825d542c32ad69eb906562e 100644 (file)
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -2,8 +2,8 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import freechips.rocketchip.chip.RTCPeriod
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex.RTCPeriod
 import freechips.rocketchip.diplomacy.DTSTimebase
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
@@ -205,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
   val rxm = Module(new UARTRx(params))
   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 
-  val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200
+  val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
   val div = Reg(init = UInt(divinit, uartDivisorBits))
 
   private val stopCountBits = log2Up(uartStopBits)

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index b070a42a27b9e3c954f555aae884a66c2f22845e..c925a38a0e47307e281788a7e30abb195ab8eb27 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -3,20 +3,19 @@ package sifive.blocks.devices.uart
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
-trait HasPeripheryUART extends HasSystemNetworks {
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
   val uartParams = p(PeripheryUARTKey)  
   val uarts = uartParams map { params =>
-    val uart = LazyModule(new TLUART(peripheryBusBytes, params))
-    uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := uart.intnode
+    val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+    uart.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := uart.intnode
     uart
   }
 }

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 9567f56a07d1fa3cbbab393c2b8b701b541f0348..afaff337e3d67a340ae1b245e5f948ebd12f65a2 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -4,9 +4,8 @@ package sifive.blocks.devices.xilinxvc707mig
 import Chisel._
 import chisel3.experimental.{Analog,attach}
 import freechips.rocketchip.amba.axi4._
-import freechips.rocketchip.chip._
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.coreplex.CacheBlockBytes
+import freechips.rocketchip.coreplex._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index 540821ecc4b336e90ede107e73851cd088b2edce..068f64cbd3a16987cbe6948202e762c0b7903039 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -2,27 +2,28 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
+import freechips.rocketchip.coreplex.HasMemoryBus
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
 
-trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
-  val module: HasPeripheryXilinxVC707MIGModuleImp
+trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
+  val module: HasMemoryXilinxVC707MIGModuleImp
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
+
   require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  xilinxvc707mig.node := mem(0).node
+  xilinxvc707mig.node := memBuses.head.toDRAMController
 }
 
-trait HasPeripheryXilinxVC707MIGBundle {
+trait HasMemoryXilinxVC707MIGBundle {
   val xilinxvc707mig: XilinxVC707MIGIO
   def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
     pads <> xilinxvc707mig
   }
 }
 
-trait HasPeripheryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
-    with HasPeripheryXilinxVC707MIGBundle {
-  val outer: HasPeripheryXilinxVC707MIG
+trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
+    with HasMemoryXilinxVC707MIGBundle {
+  val outer: HasMemoryXilinxVC707MIG
   val xilinxvc707mig = IO(new XilinxVC707MIGIO)
 
   xilinxvc707mig <> outer.xilinxvc707mig.module.io.port

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 008556a9a55d52d79c7caefe668be9ccdcebadda..b55ec4ddcf1d47d3e181620d5379ee2d7136bc62 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -2,31 +2,28 @@
 package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
+import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink._
 
-trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
+trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  private val intXing = LazyModule(new IntXing)
 
-  fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
-  xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
-  xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
-  intBus.intnode := intXing.intnode
-  intXing.intnode := xilinxvc707pcie.intnode
+  sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
+  xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
+  xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
+  ibus.fromAsync := xilinxvc707pcie.intnode
 }
 
-trait HasPeripheryXilinxVC707PCIeX1Bundle {
+trait HasSystemXilinxVC707PCIeX1Bundle {
   val xilinxvc707pcie: XilinxVC707PCIeX1IO
   def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
     pads <> xilinxvc707pcie
   }
 }
 
-trait HasPeripheryXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
-    with HasPeripheryXilinxVC707PCIeX1Bundle {
-  val outer: HasPeripheryXilinxVC707PCIeX1
+trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+    with HasSystemXilinxVC707PCIeX1Bundle {
+  val outer: HasSystemXilinxVC707PCIeX1
   val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
 
   xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port