move FU IntegerData to directory below

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 32e2944a3fb1a092c59d0b9772d07110013e4c46..768d6a444c17283339bf7add42e7913d14a5ce29 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,26 +1,11 @@
 from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.pipe_data import IntegerData
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
 
 
-class IntegerData:
-
-    def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.ctx
-
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
-
-    def ports(self):
-        return self.ctx.ports()
-
-
 class ALUInputData(IntegerData):
     regspec = [('INT', 'a', '0:63'),
                ('INT', 'b', '0:63'),

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 13179c8f13572205dfee7a953efdc17671abeab8..80b601e141a7edaa47f5336238d7ae4a8303db09 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -26,7 +26,7 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.pipe_data import IntegerData
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
 

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index a6cd835e9b3886224d783227b973f04fec363b29..7a9e4422b824a605a9a8f39cae689f8d1dfd5a0f 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -1,6 +1,6 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.pipe_data import IntegerData
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
 

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 256317cb62012c90ba4b865b1545786b872ca17b..eb01271351c08222a1e5d7b88593befe6b037bf7 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,6 +1,7 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData, ALUOutputData
+from soc.fu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import ALUOutputData
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
 

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index c14f6a08402f6a89b4aac83ce3f3763ba697c1b5..a676e8f6020b829d72ae3a28f4e347366ef1a1b0 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -11,9 +11,8 @@ from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
-
 from soc.fu.logical.pipeline import LogicalBasePipe
-from soc.fu.alu.pipe_data import LogicalPipeSpec
+from soc.fu.logical.pipe_data import LogicalPipeSpec
 import random
 
 

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
new file mode 100644 (file)
index 0000000..764de09
--- /dev/null
+++ b/src/soc/fu/pipe_data.py
@@ -0,0 +1,17 @@
+from ieee754.fpcommon.getop import FPPipeContext
+
+
+class IntegerData:
+
+    def __init__(self, pspec):
+        self.ctx = FPPipeContext(pspec)
+        self.muxid = self.ctx.muxid
+
+    def __iter__(self):
+        yield from self.ctx
+
+    def eq(self, i):
+        return [self.ctx.eq(i.ctx)]
+
+    def ports(self):
+        return self.ctx.ports()

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 3937052201ca1f684e6b458352100acf36fb8e71..29f07efc4ac2b7f5164821db7de6d3e42fe8c130 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -2,7 +2,8 @@ from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import ALUOutputData, IntegerData
+from soc.fu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import ALUOutputData
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 
 

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index af0e9d7a08bbbb220fd581181a1e19cf10163014..de930da318b94ab6be0686fffac360e134a60839 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -1,6 +1,6 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.pipe_data import IntegerData
 from soc.decoder.power_decoder2 import Data
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace