output registers need to be Data type (consistently)

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 42bea516e49d7967026e6dd08ed23d5a7b302116..cdd5c97a12e0876462caa7c25564ea3a1ca1d23b 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -39,7 +39,7 @@ class ALUOutputData(IntegerData):
                ('XER', 'xer_so', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.o = Signal(64, reset_less=True, name="stage_o")
+        self.o = Data(64, name="stage_o")
         self.cr0 = Data(4, name="cr0")
         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 0eae72f0509cb0bfa7ed7c9367909fb0e19770e4..4b736a0b85c3176c6616c9d1023fe5db67c2ec04 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -50,7 +50,7 @@ class CROutputData(IntegerData):
                ('CR', 'cr_o', '0:3')]     # 4 bit range
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.o = Signal(64, reset_less=True) # RA
+        self.o = Data(64, name="o") # RA
         self.full_cr = Data(32, name="cr_out") # CR in
         self.cr_o = Data(4, name="cr_o")
 
@@ -66,6 +66,7 @@ class CROutputData(IntegerData):
                       self.full_cr.eq(i.full_cr),
                       self.cr_o.eq(i.cr_o)]
 
+
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)
     opsubsetkls = CompCROpSubset

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 9ded5f4ad357f129d1f5d6fcad51c16785db8479..7113773337798eb62bc082ddb0acde56deba91da 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -35,7 +35,7 @@ class LogicalOutputData(IntegerData):
                ('XER', 'xer_so', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.o = Signal(64, reset_less=True, name="stage_o")
+        self.o = Data(64, name="stage_o")  # RT
         self.cr0 = Data(4, name="cr0")
         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
         self.xer_so = Data(1, name="xer_so")