litex expects wishbone "err" signals even if not used

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 07a460e3a1ac84ac7c28dd9def699f86b4a6633d..72b432da27f4ec5b807d4367ac96eac7af6dc214 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -85,7 +85,8 @@ class TestIssuerInternal(Elaboratable):
         if self.sram4x4k:
             self.sram4k = []
             for i in range(4):
-                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
+                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
+                                                    features={'err'}))
 
         # add interrupt controller?
         self.xics = hasattr(pspec, "xics") and pspec.xics == True