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also add blackboxes spblock512* etc.
[soclayout.git]
/
experiments10
/
2021-04-12
Luke Kenneth Casso...
rename JTAG port in adder test experiments10_verilog...
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commitdiff
2021-04-01
Luke Kenneth Casso...
run doChipFloorplan in experiments10
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commitdiff
2021-04-01
Luke Kenneth Casso...
increase experiment10 JTAG tap width to 4
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commitdiff
2020-11-12
Luke Kenneth Casso...
remove io_in/io_out from niolib experiments10
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commitdiff
2020-11-04
Luke Kenneth Casso...
minor reformat of spec, whitespace
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2020-11-02
Jean-Paul Chaput
Completed experiment10, adder with JTAG (dual clocks...
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commitdiff
2020-10-25
Jean-Paul Chaput
Added one-clock generated add.vst.
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commitdiff
2020-10-25
Jean-Paul Chaput
Experiment10 switched to the new chip2core module.
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commitdiff
2020-10-25
Luke Kenneth Casso...
update non_generated add.il for convenience
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commitdiff
2020-10-24
Luke Kenneth Casso...
add feedback shift register back in
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commitdiff
2020-10-22
Luke Kenneth Casso...
add non-generated add.il
tree
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commitdiff
2020-10-22
Luke Kenneth Casso...
add jtag IO to experiment10
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commitdiff
2020-10-22
Luke Kenneth Casso...
add JTAG test
tree
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commitdiff
2020-10-22
Luke Kenneth Casso...
add experiments10, to add C4M JTAG
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commitdiff