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Added support files for ls180+SRAM on TSMC 180nm.
[soclayout.git]
/
experiments9
/
coriolis2
/
2020-11-08
Luke Kenneth Casso...
start conversion of ls180 to new niolib
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2020-11-05
Luke Kenneth Casso...
update to "full" core
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2020-10-04
Luke Kenneth Casso...
match up power/gnd numbers with pinmux
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2020-10-04
Luke Kenneth Casso...
use new extpower/intpower and pads.useCoreSize params
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2020-10-02
Luke Kenneth Casso...
really really cut down core
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2020-10-02
Luke Kenneth Casso...
move ioring to pinmux
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2020-10-01
Luke Kenneth Casso...
sort sys_* pad names
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2020-10-01
Luke Kenneth Casso...
add I2C, allow sys_clk_i and sys_pll_48_o out
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2020-09-30
Luke Kenneth Casso...
increase core.size to 27500x27500
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2020-09-30
Luke Kenneth Casso...
commented-out core.size and chip.size which would allow the
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2020-09-29
Luke Kenneth Casso...
add cki and ck to clock settings
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2020-09-28
Luke Kenneth Casso...
add sdram_dm_1 back in
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2020-09-28
Luke Kenneth Casso...
iopad pads.instances mapping
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2020-09-28
Luke Kenneth Casso...
cut definition of clocks back to minimum
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2020-09-28
Luke Kenneth Casso...
connect up dummy "NC" pins
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2020-09-27
Luke Kenneth Casso...
add soc ioring
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2020-08-13
Luke Kenneth Casso...
whitespace cleanup
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2020-08-13
Luke Kenneth Casso...
whoops must use "with" on CfgCache
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2020-08-12
Jean-Paul Chaput
Added doDesignFlat.py to P&R issuer in a flat way.
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2020-08-11
Jean-Paul Chaput
Correct taking in accounts of the parameters settings.
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2020-08-11
Luke Kenneth Casso...
fix coriolis2 settings to use new CfgCache
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2020-08-07
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2020-08-07
Jean-Paul Chaput
Use of CfgCache. Little beautificaton of doDesign.py
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2020-08-03
Jean-Paul Chaput
Fisrt attempt at floorplaning test_issuer.
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2020-06-30
Jean-Paul Chaput
Added experments9, a first taste at the full scale...
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