sv_binutils: discard VHDL stuff in comments
[openpower-isa.git] / openpower / isatables /
2022-01-06 Jacob Lifshayadd grev[w][i] instructions
2022-01-06 Luke Kenneth Casso... add tlbsync and wait as NOPs
2022-01-05 Luke Kenneth Casso... add eieio instruction as a NOP to minor 31 csv
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-10 Jacob Lifshayadd .gitignore to ignore the generated vhdl
2021-12-02 Jacob Lifshaymove ternlogi to SHIFT_ROT unit
2021-11-17 Jacob Lifshayrename ternary->ternlog and associated form/field TI...
2021-11-13 Jacob Lifshayremove excess I from ternary-related names
2021-11-12 Jacob Lifshaychange ternaryi to correct register fields
2021-11-05 Jacob Lifshayadd ternaryi
2021-11-05 Jacob Lifshayadd comment2 and unofficial fields to existing instructions
2021-11-04 Tobias Platendcbz needs to go through ldst function unit
2021-08-08 Luke Kenneth Casso... add bc and bclr to sv_analysis
2021-08-07 Luke Kenneth Casso... remove SVP64 Branch format modifications (achieve a...
2021-08-05 Luke Kenneth Casso... add SVP64 Branch-Conditional equivalent of Rc fields
2021-08-01 Luke Kenneth Casso... add BCD operations to SVP64
2021-07-30 Dmitry Selyutinisatables: cbcdtd instruction
2021-07-30 Dmitry Selyutinisatables: cdtbcd instruction
2021-07-27 Dmitry Selyutinisatables: addg6s instruction
2021-07-27 Luke Kenneth Casso... fix errors in detection of ffmadds (etc), enabling...
2021-07-24 Luke Kenneth Casso... added an extra SVP64 instruction, svstep, to replace...
2021-07-23 Luke Kenneth Casso... add sv.fdmadds unit test
2021-07-23 Luke Kenneth Casso... add DCT mul-add to CSV and enums
2021-07-20 Luke Kenneth Casso... realised that SVSHAPE0-3 is not privileged
2021-07-16 Luke Kenneth Casso... add fsins and fcoss to simulator
2021-07-15 Luke Kenneth Casso... add extra "persistence" bit to svremap instruction
2021-07-15 Luke Kenneth Casso... big intrusive update: merge SVREMAP with SVSTATE, remov...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length
2021-07-11 Luke Kenneth Casso... minor reordering of setvl and svshape: svshape is now...
2021-07-11 Luke Kenneth Casso... update svremap instruction to correctly store immediate...
2021-07-11 Luke Kenneth Casso... whoops 0b00002 is not binary
2021-07-11 Luke Kenneth Casso... add SVREMAP new Form / Fields and CSV entry
2021-07-11 Luke Kenneth Casso... add SVREMAP SPR
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
2021-07-10 Luke Kenneth Casso... add ffadds decoding:
2021-07-08 Luke Kenneth Casso... add in extra "vertical" mode into SVP64 setvl
2021-07-06 Luke Kenneth Casso... add FFT REMAP butterfly unit test
2021-07-05 Luke Kenneth Casso... fix svremap field offsets
2021-07-05 Luke Kenneth Casso... add svremap manual instruction (Primary Opcode 22,...
2021-07-01 Luke Kenneth Casso... add TEMPORARY svremap form and instruction
2021-06-27 Luke Kenneth Casso... add new (experimental) ffmadds and ffmsubs, for FFT...
2021-06-27 Luke Kenneth Casso... change name to OP_FP_MADD to identify fmadd (etc)
2021-06-27 Luke Kenneth Casso... add SVP64 FFT mode to PowerDecoder, add CSV entries
2021-06-26 Luke Kenneth Casso... use If Elif in power_decoder conditions, a lot easier...
2021-06-26 Luke Kenneth Casso... rename bit-reversed LDs to match v3.0B (strip "br")
2021-06-25 Luke Kenneth Casso... identify SVP64 LD bit-reverse pattern as pseudo-assembler
2021-06-25 Luke Kenneth Casso... update sv_analysis.py to match new CONDITIONs field...
2021-06-24 Luke Kenneth Casso... add major.csv LD operations with SVP64BREV condition
2021-06-24 Luke Kenneth Casso... add extra CONDITION column to CSVs
2021-06-23 Luke Kenneth Casso... only add SVP64 bitreverse mode for LDs at the moment...
2021-06-23 Luke Kenneth Casso... add SVP64 LD/ST "bitrev" alternative CSV
2021-06-23 Luke Kenneth Casso... add sv bitrev "major" CSV table
2021-06-23 Luke Kenneth Casso... add SVD-Form and SVDS-Form, variants of fixedload for...
2021-06-18 Luke Kenneth Casso... add SV Context SPRs (SVCTX0-7)
2021-06-18 Luke Kenneth Casso... add SVR-Form and associated fields
2021-06-18 Luke Kenneth Casso... add four SVSHAPE SPRs for REMAP
2021-06-17 Luke Kenneth Casso... add SV "Context Propagation" Form
2021-06-15 Luke Kenneth Casso... fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsub...
2021-05-19 Luke Kenneth Casso... resolve merge conflicts, effectively reverting "verbose...
2021-05-19 Luke Kenneth Casso... corrections to stf/lf RA_OR_ZERO not in all cases
2021-05-18 Luke Kenneth Casso... fix SVP64 EXTRA2/3 decode for IEEE754 FP LD/ST operations
2021-05-18 Luke Kenneth Casso... add beginning support for SVP64 IEEE754 FP
2021-05-15 Luke Kenneth Casso... add minor_59.csv file, corrected, and power enums
2021-05-15 Luke Kenneth Casso... issue with sub-decoders
2021-05-15 Luke Kenneth Casso... add X-Form and A-Form to minor_63l and minor_63h csv...
2021-05-15 Luke Kenneth Casso... whoops need to reverse bits in minor_63l.csv to match...
2021-05-15 Luke Kenneth Casso... FP 63L/H ops need to add in extra 0/1 minor_63l.csv...
2021-05-15 Luke Kenneth Casso... add FP LD/ST D-Form operations to major.csv
2021-05-15 Luke Kenneth Casso... add load/store FP indexed instructions to minor_31.csv
2021-05-14 Luke Kenneth Casso... add FRA ISACaller name decoding
2021-04-23 Luke Kenneth Casso... add isatables extracted from microwatt and v3.0B spec