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corrections to shift_down and is_overflow, test "1.0 + 2.0 == 3.0" works
[ieee754fpu.git]
/
src
/
add
/
nmigen_add_experiment.py
2019-02-15
Luke Kenneth Casso...
corrections to shift_down and is_overflow, test "1...
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2019-02-15
Luke Kenneth Casso...
lots and lots of debugging corrections...
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2019-02-15
Luke Kenneth Casso...
corrections from running simulation
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2019-02-14
Luke Kenneth Casso...
add verilog conversion (commented out)
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2019-02-14
Luke Kenneth Casso...
corrections
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2019-02-14
Luke Kenneth Casso...
remove verilog
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2019-02-14
Luke Kenneth Casso...
corrections, out_z_* and friends are members of class
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2019-02-14
Luke Kenneth Casso...
add in a "corrections" stage, small rework, split pack...
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2019-02-14
Aleksandar Kostovic
Translate put_z verilog case into nmigen
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2019-02-14
Luke Kenneth Casso...
add and use is_overflowed function
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2019-02-14
Luke Kenneth Casso...
cleanup
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2019-02-14
Luke Kenneth Casso...
document guard/round/sticky and tot
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2019-02-14
Aleksandar Kostovic
Translate case from verilog to nmigen
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2019-02-14
Luke Kenneth Casso...
add code comments
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2019-02-14
Luke Kenneth Casso...
add set-to-zero function
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2019-02-14
Luke Kenneth Casso...
fix bug in nan/inf, exp-bias needed subtracting
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2019-02-14
Luke Kenneth Casso...
add FPNum comment
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2019-02-14
Luke Kenneth Casso...
add comments for aleksander
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2019-02-14
Luke Kenneth Casso...
add comments for aleksander
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2019-02-14
Luke Kenneth Casso...
use negative slice (now works)
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2019-02-14
Luke Kenneth Casso...
remove a_s/b_s/z_s
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2019-02-14
Luke Kenneth Casso...
move align down-shift to separate function
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2019-02-14
Luke Kenneth Casso...
move +127 for exponent bias into FPNum.create
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2019-02-14
Luke Kenneth Casso...
remove unneeded code
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2019-02-14
Luke Kenneth Casso...
comments
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2019-02-14
Luke Kenneth Casso...
add zero, nan and inf checks
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2019-02-14
Luke Kenneth Casso...
create and use decode function
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2019-02-14
Luke Kenneth Casso...
move create, inf and nan to FPNum class
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2019-02-14
Luke Kenneth Casso...
create FPNum class
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2019-02-14
Luke Kenneth Casso...
add rounding stage
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2019-02-14
Luke Kenneth Casso...
add comments
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2019-02-14
Luke Kenneth Casso...
add normalise_1 stage
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2019-02-14
Luke Kenneth Casso...
add NaN and INF functions
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2019-02-14
Aleksandar Kostovic
Merge branch 'master' of ssh://libre-riscv.org:922...
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2019-02-14
Aleksandar Kostovic
Turned the normalise_2 verilog state into nmigen
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2019-02-14
Luke Kenneth Casso...
use function "create_z" which... well... creates a...
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2019-02-14
Luke Kenneth Casso...
add in comments on add 2nd stage
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2019-02-14
Luke Kenneth Casso...
off-by-one in slices
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2019-02-14
Aleksandar Kostovic
Merge branch 'master' of ssh://libre-riscv.org:922...
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2019-02-14
Aleksandar Kostovic
Turned the add_1 verilog state into nmigen
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2019-02-14
Luke Kenneth Casso...
corrections on compile
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2019-02-14
Luke Kenneth Casso...
add align phase
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2019-02-14
Luke Kenneth Casso...
whoops accidentally indented too far
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2019-02-14
Luke Kenneth Casso...
add code comments
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2019-02-14
Luke Kenneth Casso...
reformat / indent add_0 stage
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2019-02-14
Aleksandar Kostovic
Turned the add_0 verilog state into nmigen
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2019-02-14
Luke Kenneth Casso...
add zero and denormalised checks
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2019-02-14
Luke Kenneth Casso...
add special case, b when a is zero
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2019-02-14
Luke Kenneth Casso...
add b inf special case
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2019-02-14
Luke Kenneth Casso...
cleanup and comments
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2019-02-14
Luke Kenneth Casso...
add inf special case
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2019-02-14
Luke Kenneth Casso...
whitespace (indent)
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2019-02-14
Luke Kenneth Casso...
add first of special_cases
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2019-02-14
Luke Kenneth Casso...
invert Cat order, use 3 zeros (3 bits)
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2019-02-14
Luke Kenneth Casso...
spelling correction
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2019-02-14
Luke Kenneth Casso...
corrected syntax for unpack block
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2019-02-13
Aleksandar Kostovic
Replicated unpack part of always block into nmigen
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2019-02-13
Luke Kenneth Casso...
add experiment
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