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adapt TRAP function in main state pipeline to put KAIVB
[soc.git]
/
src
/
soc
/
bus
/
external_core.py
2022-02-15
Luke Kenneth Casso...
update comments
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2022-02-14
Luke Kenneth Casso...
strip first 3 bits of WB address from microwatt d/i...
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2022-02-14
Luke Kenneth Casso...
sort out ExternalCore signal names
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2022-02-14
Luke Kenneth Casso...
add external core verilog wrapper, ironically around...
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