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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
bus
/ tercel.py
2022-04-06
Luke Kenneth Casso...
only add clock-settings on ECP5 due to special SPI...
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2022-04-04
Luke Kenneth Casso...
allow direction-setting on each of dq0-3 in Tercel...
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2022-03-31
Luke Kenneth Casso...
invert cs_n pin in Tercel
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2022-03-30
Luke Kenneth Casso...
nope, default features in Tercel WB Buses need to not...
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2022-03-29
Luke Kenneth Casso...
add bus.err to list of default Wishbone signals in...
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2022-03-29
Luke Kenneth Casso...
byte-reverse Tercel read/write data and config bus...
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2022-03-29
Luke Kenneth Casso...
set clock freq Constant length to 32-bit in Tercel.
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2022-03-29
Luke Kenneth Casso...
self.specials does not exist, Instances must be added...
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2022-03-29
Luke Kenneth Casso...
more sorting out wishbone names in Tercel
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2022-03-29
Luke Kenneth Casso...
fix names of Instance signals in Tercel
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2022-03-29
Luke Kenneth Casso...
sort out variable names in Tercel
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2022-03-29
Luke Kenneth Casso...
self.comb does not exist, comb is a local temp-var...
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2022-03-18
Luke Kenneth Casso...
whitespace cleanup (80 char limit, pep8)
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2022-03-16
Raptor Engineering...
Add initial Tercel integration
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