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start decoding sv EXTRAs and identifying them
[soc.git]
/
src
/
soc
/
clock
/
dummypll.py
2020-11-13
Luke Kenneth Casso...
reduce clkcsel ls180 width (2 pins), rename pll_18...
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2020-11-13
Luke Kenneth Casso...
rename and add pll lock signal to ls180
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2020-11-10
Luke Kenneth Casso...
remove ClockSelect module, use DummyPLL
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2020-11-10
Luke Kenneth Casso...
add separate DummyPLL module, according to API discussed at
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projects / soc.git / history