move over to from openpower imports
[soc.git] / src / soc / experiment / compalu.py
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-05-24 Cesar StraussRename the internal DFF of latchregisters to avoid...
2020-04-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-17 Luke Kenneth Casso... not using relative imports (pain in the neck)
2020-04-17 Jacob Lifshayfix tests
2020-04-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-11 Luke Kenneth Casso... pass and lock immediate in
2020-04-11 Luke Kenneth Casso... adding immediates, tracking down a bug
2020-04-09 Luke Kenneth Casso... get CompUnitALU test running with InternalOp ALU subset
2020-04-09 Luke Kenneth Casso... experiment morphing ALU to take subset of Decode2ToExecute1
2020-04-08 Luke Kenneth Casso... pass InternalOp through to CompUnit ALU
2020-04-08 Luke Kenneth Casso... whoops realised src1/2 need to receive reg data, not...
2020-04-08 Luke Kenneth Casso... start using power decoder in 6600 comp units
2020-03-10 Luke Kenneth Casso... add "done" signal to CompALU and LDSTCompALU to be...
2020-03-09 Luke Kenneth Casso... move all source directories to soc so that "import...