src/soc/experiment/compalu.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6 from soc.decoder.power_decoder2 import Data
   7 from soc.decoder.power_enums import InternalOp
   8
   9
  10 """ Computation Unit (aka "ALU Manager").
  11
  12     This module runs a "revolving door" set of three latches, based on
  13     * Issue
  14     * Go_Read
  15     * Go_Write
  16     where one of them cannot be set on any given cycle.
  17     (Note however that opc_l has been inverted (and qn used), due to SRLatch
  18      default reset state being "0" rather than "1")
  19
  20     * When issue is first raised, a busy signal is sent out.
  21       The src1 and src2 registers and the operand can be latched in
  22       at this point
  23
  24     * Read request is set, which is acknowledged through the Scoreboard
  25       to the priority picker, which generates (one and only one) Go_Read
  26       at a time.  One of those will (eventually) be this Computation Unit.
  27
  28     * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
  29       src1/src2/operand in place), and the ALU is told to proceed.
  30
  31     * As this is currently a "demo" unit, a countdown timer is activated
  32       to simulate an ALU "pipeline", which activates "write request release",
  33       and the ALU's output is captured into a temporary register.
  34
  35     * Write request release will go through a similar process as Read request,
  36       resulting (eventually) in Go_Write being asserted.
  37
  38     * When Go_Write is asserted, two things happen: (1) the data in the temp
  39       register is placed combinatorially onto the output, and (2) the
  40       req_l latch is cleared, busy is dropped, and the Comp Unit is back
  41       through its revolving door to do another task.
  42
  43     Notes on oper_i:
  44
  45     * bits[0:2] are for the ALU, add=0, sub=1, shift=2, mul=3
  46     * bit[2] are the immediate (bit[2]=1 == immediate mode)
  47 """
  48
  49 class ComputationUnitNoDelay(Elaboratable):
  50     def __init__(self, rwid, e, alu):
  51         self.rwid = rwid
  52         self.alu = alu # actual ALU - set as a "submodule" of the CU
  53         self.e = e # decoded instruction
  54
  55         self.counter = Signal(4)
  56         self.go_rd_i = Signal(reset_less=True) # go read in
  57         self.go_wr_i = Signal(reset_less=True) # go write in
  58         self.issue_i = Signal(reset_less=True) # fn issue in
  59         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  60         self.go_die_i = Signal() # go die (reset)
  61
  62         # operation / data input
  63         self.oper_i = e.insn_type    # operand
  64         self.imm_i =  e.imm_data      # immediate in
  65         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  66         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  67
  68         self.busy_o = Signal(reset_less=True) # fn busy out
  69         self.data_o = Signal(rwid, reset_less=True) # Dest out
  70         self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
  71         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
  72         self.done_o = self.req_rel_o # 'normalise' API
  73
  74     def elaborate(self, platform):
  75         m = Module()
  76         m.submodules.alu = self.alu
  77         m.submodules.src_l = src_l = SRLatch(sync=False)
  78         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  79         m.submodules.req_l = req_l = SRLatch(sync=False)
  80
  81         # shadow/go_die
  82         reset_w = Signal(reset_less=True)
  83         reset_r = Signal(reset_less=True)
  84         m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
  85         m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
  86
  87         # This is fascinating and very important to observe that this
  88         # is in effect a "3-way revolving door".  At no time may all 3
  89         # latches be set at the same time.
  90
  91         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
  92         m.d.sync += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
  93         m.d.sync += opc_l.r.eq(reset_w)      # XXX NOTE: INVERTED FROM book!
  94
  95         # src operand latch (not using go_wr_i)
  96         m.d.sync += src_l.s.eq(self.issue_i)
  97         m.d.sync += src_l.r.eq(reset_r)
  98
  99         # dest operand latch (not using issue_i)
 100         m.d.sync += req_l.s.eq(self.go_rd_i)
 101         m.d.sync += req_l.r.eq(reset_w)
 102
 103         # create a latch/register for the operand
 104         oper_r = Signal(InternalOp, reset_less=True) # opcode reg
 105         latchregister(m, self.oper_i, oper_r, self.issue_i)
 106
 107         # and one for the output from the ALU
 108         data_r = Signal(self.rwid, reset_less=True) # Dest register
 109         latchregister(m, self.alu.o, data_r, req_l.q)
 110
 111         # get the top 2 bits for the ALU
 112         m.d.comb += self.alu.op.eq(oper_r[0:2])
 113
 114         # 3rd bit is whether this is an immediate or not
 115         op_is_imm = Signal(reset_less=True)
 116         m.d.comb += op_is_imm.eq(oper_r[2])
 117
 118         # select immediate if opcode says so.  however also change the latch
 119         # to trigger *from* the opcode latch instead.
 120         src2_or_imm = Signal(self.rwid, reset_less=True)
 121         src_sel = Signal(reset_less=True)
 122         m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.qn, src_l.q))
 123         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i, self.src2_i))
 124
 125         # create a latch/register for src1/src2
 126         latchregister(m, self.src1_i, self.alu.a, src_l.q)
 127         latchregister(m, src2_or_imm, self.alu.b, src_sel)
 128
 129         # -----
 130         # outputs
 131         # -----
 132
 133         # all request signals gated by busy_o.  prevents picker problems
 134         busy_o = self.busy_o
 135         m.d.comb += busy_o.eq(opc_l.q) # busy out
 136         m.d.comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
 137
 138         # on a go_read, tell the ALU we're accepting data.
 139         # NOTE: this spells TROUBLE if the ALU isn't ready!
 140         # go_read is only valid for one clock!
 141         with m.If(self.go_rd_i):                     # src operands ready, GO!
 142             with m.If(~self.alu.p_ready_o):          # no ACK yet
 143                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 144
 145         # only proceed if ALU says its output is valid
 146         with m.If(self.alu.n_valid_o):
 147             # when ALU ready, write req release out. waits for shadow
 148             m.d.comb += self.req_rel_o.eq(req_l.q & busy_o & self.shadown_i)
 149             # when output latch is ready, and ALU says ready, accept ALU output
 150             with m.If(self.req_rel_o):
 151                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 152
 153         # output the data from the latch on go_write
 154         with m.If(self.go_wr_i):
 155             m.d.comb += self.data_o.eq(data_r)
 156
 157         return m
 158
 159     def __iter__(self):
 160         yield self.go_rd_i
 161         yield self.go_wr_i
 162         yield self.issue_i
 163         yield self.shadown_i
 164         yield self.go_die_i
 165         yield self.oper_i
 166         yield from self.imm_i.ports()
 167         yield self.src1_i
 168         yield self.src2_i
 169         yield self.busy_o
 170         yield self.rd_rel_o
 171         yield self.req_rel_o
 172         yield self.data_o
 173
 174     def ports(self):
 175         return list(self)
 176
 177
 178 def scoreboard_sim(dut):
 179     yield dut.dest_i.eq(1)
 180     yield dut.issue_i.eq(1)
 181     yield
 182     yield dut.issue_i.eq(0)
 183     yield
 184     yield dut.src1_i.eq(1)
 185     yield dut.issue_i.eq(1)
 186     yield
 187     yield
 188     yield
 189     yield dut.issue_i.eq(0)
 190     yield
 191     yield dut.go_read_i.eq(1)
 192     yield
 193     yield dut.go_read_i.eq(0)
 194     yield
 195     yield dut.go_write_i.eq(1)
 196     yield
 197     yield dut.go_write_i.eq(0)
 198     yield
 199
 200 def test_scoreboard():
 201     from alu_hier import ALU
 202     from soc.decoder.power_decoder2 import Decode2ToExecute1Type
 203
 204     e = Decode2ToExecute1Type()
 205     alu = ALU(16)
 206     dut = ComputationUnitNoDelay(16, e, alu)
 207     vl = rtlil.convert(dut, ports=dut.ports())
 208     with open("test_compalu.il", "w") as f:
 209         f.write(vl)
 210
 211     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
 212
 213 if __name__ == '__main__':
 214     test_scoreboard()